AD9736BBC datasheet(35/72 Pages) AD

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AD9734/AD9735/AD9736

Rev. A | Page 35 of 72

THEORY OF OPERATION

The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and

10-bit DACs that run at an update rate up to 1.2 GSPS. Input

data can be accepted up to the full 1.2 GSPS rate, or a 2×

interpolation filter can be enabled (2× mode) allowing full

speed operation with a 600 MSPS input data rate. The DATA

and DATACLK_IN inputs are parallel LVDS, meeting the IEEE

reduced swing LVDS specifications with the exception of input

hysteresis. The DATACLK_IN input runs at one-half the input

DATA rate in a double data rate (DDR) format. Each edge of

DATACLK_IN transfers DATA into the AD9736, as shown in

Figure 79.

The DACCLK−/DACCLK+ inputs (Pin E1 and Pin F1) directly

drive the DAC core to minimize clock jitter. The DACCLK

signal is also divided by 2 (1× and 2× mode), then output as the

DATACLK_OUT. The DATACLK_OUT signal clocks the data

source. The DAC expects DDR LVDS data (DB<13:0>) aligned

with the DDR input clock (DATACLK_IN) from a circuit simi-

lar to the one shown in Figure 96. Table 19 shows the clock

relationships.

Table 19. AD973x Clock Relationship

MODE

DACCLK

DATACLK_OUT

DATACLK_IN

DATA

1×

1.2 GHz

600 MHz

1.2 GSPS

2×

1.2 GHz

600 MHz

300 MHz

600 MSPS

Maintaining correct alignment of data and clock is a common

challenge with high speed DACs, complicated by changes in

temperature and other operating conditions. Using the

DATACLK_OUT signal to generate the data allows most of the

internal process, temperature, and voltage delay variation to be

cancelled. The AD973x further simplifies this high speed data

capture problem with two adaptive closed-loop timing

controllers.

One timing controller manages the LVDS data and data clock

alignment (LVDS controller), and the other manages the LVDS

data and DACCLK alignment (sync controller).

The LVDS controller locates the data transitions and delays the

DATACLK_IN so that its transition is in the center of the valid

data window. The sync controller manages the FIFO that moves

data from the LVDS DATACLK_IN domain to the DACCLK

domain.

Both controllers can operate in manual mode under external

processor control, in surveillance mode where error conditions

generate external interrupts, or in automatic mode where errors

are automatically corrected.

The LVDS and sync controllers include moving average filtering

for noise immunity and variable thresholds to control activity.

Normally, the controllers are set to run in automatic mode,

making any necessary adjustments without dropping or dupli-

cating samples sent to the DAC. Both controllers require initial

calibration prior to entering automatic update mode.

The AD973x analog output changes 35 DACCLK cycles after

the input data changes in 1× mode with the FIFO disabled. The

FIFO adds up to eight additional cycles of delay. This delay is

read from the SPI port. Internal clock delay variation is less

than a single DACCLK cycle at 1.2 GHz (833 ps).

Stopping the AD973x DATACLK_IN while the DACCLK is still

running can lead to unpredictable output signals. This occurs

because the internal digital signal path is interleaved. The last

two samples clocked into the DAC continue to be clocked out

by DACCLK even after DATACLK_IN has stopped. The result-

ing output signal is at a frequency of one-half fDAC, and the

amplitude depends on the difference between the last two

samples.

Control of the AD973x functions is via the serially programmed

registers listed in Table 9. Optionally, a limited number of func-

tions can be directly set by external pins in pin mode.

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