LPC1850_13 datasheet(72/149 Pages) NXP

72 / 149 page

LPC1850_30_20_10

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Product data sheet

Rev. 6.1 — 7 February 2013

72 of 149

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals.

• Supports all full-speed USB-compliant peripherals.

• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for OTG peripherals.

• Supports interrupts.

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.13.7 High-speed USB Host/Device interface with ULPI (USB1)

Remark: USB1 is available on parts LPC1850/30 (see Table 2).

The USB1 interface can operate as a full-speed USB host/device interface or can connect

to an external ULPI PHY for High-speed operation.

7.13.7.1

Features

• Complies with Universal Serial Bus specification 2.0.

• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals if connected to external ULPI

PHY.

• Supports all full-speed USB-compliant peripherals.

• Supports interrupts.

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.13.8 LCD controller

Remark: The LCD controller is available on LPC1850 only.

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024

 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

7.13.8.1

Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

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