EVAL-AD7795EB datasheet(7/36 Pages) AD

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AD7794/AD7795

Rev. D | Page 7 of 36

Parameter1

AD7794/AD7795

Unit

Test Conditions/Comments

LOGIC OUTPUT (INCLUDING CLK)

VOH, Output High Voltage2

DVDD − 0.6

V min

DVDD = 3 V, ISOURCE = 100 μA

VOL, Output Low Voltage2

0.4

V max

DVDD = 3 V, ISINK = 100 μA

VOH, Output High Voltage2

V min

DVDD = 5 V, ISOURCE = 200 μA

VOL, Output Low Voltage2

0.4

V max

DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY), 800 μA (CLK)

Floating-State Leakage Current

±10

μA max

Floating-State Output Capacitance

pF typ

Data Output Coding

Offset binary

SYSTEM CALIBRATION2

Full-Scale Calibration Limit

1.05 × FS

V max

Zero-Scale Calibration Limit

−1.05 × FS

V min

Input Span

0.8 × FS

V min

2.1 × FS

V max

POWER REQUIREMENTS7

Power Supply Voltage

AVDD to GND

2.7/5.25

V min/max

DVDD to GND

2.7/5.25

V min/max

Power Supply Currents

IDD Current

140

μA max

110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V,

unbuffered mode, external reference

185

μA max

130 μA typ @ AVDD = 3 V, 165 μA typ @ AVDD = 5 V,

buffered mode, gain = 1 or 2, external reference

400

μA max

300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V,

gain = 4 to 128, external reference

500

μA max

400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V,

gain = 4 to 128, internal reference

IDD (Power-Down Mode)

μA max

AD7794B, AD7795B

μA max

AD7794C

1 Temperature range: B Grade: −40°C to +105°C, C Grade: −40°C to +125°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-

mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AVDD – 1.6 V

typically. In addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. When this voltage is exceeded, the INL, for

example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute

voltage on the analog input pins needs to be below AVDD − 1.6 V.

2 Specification is not production tested but is supported by characterization data at initial product release.

3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

4 Recalibration at any temperature removes these errors.

5 Full-scale error applies to both positive and negative full-scale, and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C).

6 FS[3:0] are the four bits used in the mode register to select the output word rate.

7 Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.

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