TC850 datasheet(17/30 Pages) MICROCHIP

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 2001-2012 Microchip Technology Inc.

DS21479D-page 17

TC850

Figure 8-3 shows a typical interface to a

P I/O port or

single-chip

C. The TC850 operates in the Continuous

mode and can either interrupt the

C/P or be polled

with an input pin.

FIGURE 8-3:

Interface to Typical

P I/O

Port or Single Chip

C

Since the PA0-PA7 inputs are dedicated to reading A/D

data, the A/D CS/CE inputs can be enabled continu-

ously. In Continuous mode, data must be read in 3

bytes, as shown in Table 6-1. The required RD pulses

are provided by a

C/P output pin.

The circuit of Figure 8-3 can also operate in the

Demand mode, with the start-up conversion strobe

generated by a

C/P output pin. In this case, the L/H

and CONT/DEMAND inputs can be controlled by I/O

pins and the RD input connected to digital ground.

8.3

Demand Mode Interface Timing

When CONT/DEMAND input is LOW, the TC850

performs a conversion each time CE and CS are active

and WR is strobed LOW.

The Demand mode conversion timing is shown in

Figure 8-1. BUSY goes LOW and data is valid 1155

clock pulses after WR goes LOW. After BUSY goes

low, 125 additional clock cycles are required before the

next conversion cycle will begin.

Once conversion is started, WR is ignored for 1100

internal clock cycles. After 1100 clock cycles, another

WR pulse is recognized and initiates a new conversion

when the present conversion is complete. A negative

edge on WR is required to begin conversion. If WR is

held LOW, conversions will not occur continuously.

The A/D conversion data is valid on the falling edge of

BUSY and remains valid until one-half internal clock

cycle before BUSY goes HIGH on the succeeding

conversion. BUSY can be monitored with an I/O pin to

determine end of conversion or to generate a

P

interrupt.

In Demand mode, the three data bytes can be read in

any desired order. The TC850 is simply regarded as

three bytes of memory and accessed accordingly. The

bus output timing is shown in Figure 8-2.

8.4

Continuous Mode Interface Timing

When the CONT/DEMAND input is HIGH, the TC850

performs conversions continuously. Data will be valid

on the falling edge of BUSY and all three bytes must be

read within 443-1/2 internal clock cycles of BUSY going

LOW. The timing diagram is shown in Figure 8-3.

In Continuous mode, OVR/POL and L/H byte-select

inputs are ignored. The TC850 automatically cycles

through three data bytes, as shown in Table 6-1. Bus

output timing in the Continuous mode is shown in

Figure 8-4.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

BUSY

PB0

+5V

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

INTERRUPT

CONT/DEMAND

mC OR mP

I/O PORT

TC850

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