PIC24FV32KA302 datasheet(73/364 Pages) MICROCHIP

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DS39995D-page 73

PIC24FV32KA304 FAMILY

7.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer (OST) has not

expired (if a crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system.

Therefore, the oscillator and PLL start-up delays must

be considered when the Reset delay time must be

known.

7.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the

system clock source when SYSRST is released. If a

valid clock source is not available at this time, the

device will automatically switch to the FRC oscillator

and the user can switch to the desired crystal oscillator

in the Trap Service Routine (TSR).

7.3

Special Function Register Reset

States

Most of the Special Function Registers (SFRs)

associated with the PIC24F CPU and peripherals are

reset to a particular value at a device Reset. The SFRs

are grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value for

the Oscillator Control register, OSCCON, will depend on

the type of Reset and the programmed values of the

FNOSCx bits in the Flash Configuration Word

(FOSCSEL<2:0>); see Table 7-2. The RCFGCAL and

NVMCON registers are only affected by a POR.

7.4

Deep Sleep BOR (DSBOR)

Deep Sleep BOR is a very low-power BOR circuitry,

used when the device is in Deep Sleep mode. Due to

low current consumption, accuracy may vary.

The DSBOR trip point is around 2.0V. DSBOR is

enabled by configuring DSLPBOR (FDS<6>) = 1.

DSLPBOR will re-arm the POR to ensure the device will

reset if VDD drops below the POR threshold.

7.5

Brown-out Reset (BOR)

The PIC24FV32KA304 family devices implement a

BOR circuit, which provides the user several

configuration and power-saving options. The BOR is

controlled by the BORV<1:0> and BOREN<1:0>

Configuration bits (FPOR<6:5,1:0>). There are a total

of four BOR configurations, which are provided in

Table 7-3.

The BOR threshold is set by the BORV<1:0> bits. If

BOR is enabled (any values of BOREN<1:0>, except

‘00’), any drop of VDD below the set threshold point will

reset the device. The chip will remain in BOR until VDD

rises above the threshold.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above the threshold. Then, it will keep the chip

in Reset for an additional time delay, TPWRT, if VDD

drops below the threshold while the Power-up Timer is

running. The chip goes back into a BOR and the

Power-up Timer will be initialized. Once VDD rises above

the threshold, the Power-up Timer will execute the

additional time delay.

BOR and the Power-up Timer (PWRT) are indepen-

dently configured. Enabling the Brown-out Reset does

not automatically enable the PWRT.

7.5.1

SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or

disabled by the user in software. This is done with the

control bit, SBOREN (RCON<13>). Setting SBOREN

enables the BOR to function as previously described.

Clearing the SBOREN disables the BOR entirely. The

SBOREN bit operates only in this mode; otherwise, it is

read as ‘0’.

Placing BOR under software control gives the user the

additional flexibility of tailoring the application to its

environment without having to reprogram the device to

change the BOR configuration. It also allows the user

to tailor the incremental current that the BOR

consumes. While the BOR current is typically very

small, it may have some impact in low-power

applications.

Note:

Even when the BOR is under software con-

trol, the Brown-out Reset voltage level is

still set by the BORV<1:0> Configuration

bits; it cannot be changed in software.

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