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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LCMXO2-1200ZE-2TG100C датащи(PDF) 70 Page - Lattice Semiconductor |
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LCMXO2-1200ZE-2TG100C датащи(HTML) 70 Page - Lattice Semiconductor |
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70 / 106 page  3-31 DC and Switching Characteristics MachXO2 Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Descriptions Conditions Min. Max. Units fIN Input Clock Frequency (CLKI, CLKFB) 7 400 MHz fOUT Output Clock Frequency (CLKOP, CLKOS, CLKOS2) 1.5625 400 MHz fOUT2 Output Frequency (CLKOS3 cascaded from CLKOS2) 0.0122 400 MHz fVCO PLL VCO Frequency 200 800 MHz fPFD Phase Detector Input Frequency 7 400 MHz AC Characteristics tDT Output Clock Duty Cycle Without duty trim selected 3 45 55 % tDT_TRIM 7 Edge Duty Trim Accuracy -75 75 % tPH 4 Output Phase Accuracy -6 6 % tOPJIT 1, 8 Output Clock Period Jitter fOUT > 100MHz — 150 ps p-p fOUT < 100MHz — 0.007 UIPP Output Clock Cycle-to-cycle Jitter fOUT > 100MHz — 180 ps p-p fOUT < 100MHz — 0.009 UIPP Output Clock Phase Jitter fPFD > 100MHz — 160 ps p-p fPFD < 100MHz — 0.011 UIPP Output Clock Period Jitter (Fractional-N) fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP Output Clock Cycle-to-cycle Jitter (Fractional-N) fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP tSPO Static Phase Offset Divider ratio = integer -120 120 ps tW Output Clock Pulse Width At 90% or 10% 3 0.9 — ns tLOCK 2, 5 PLL Lock-in Time — 15 ms tUNLOCK PLL Unlock Time — 50 ns tIPJIT 6 Input Clock Period Jitter fPFD 20 MHz — 1,000 ps p-p fPFD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns tSTABLE 5 STANDBY High to PLL Stable — 15 ms tRST RST/RESETM Pulse Width 1 — ns tRSTREC RST Recovery Time 1 — ns tRST_DIV RESETC/D Pulse Width 10 — ns tRSTREC_DIV RESETC/D Recovery Time 1 — ns tROTATE-SETUP PHASESTEP Setup Time 10 — ns |
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