PIC16F84A_13 datasheet(32/90 Pages) MICROCHIP

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PIC16F84A

DS35007C-page 32

 2001-2013 Microchip Technology Inc.

6.11

Power-down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (wake-up from SLEEP).

6.11.1

SLEEP

The Power-down mode is entered by executing the

SLEEP

instruction.

If enabled, the Watchdog Timer is cleared (but keeps

running), the PD bit (STATUS<3>) is cleared, the TO bit

(STATUS<4>) is set, and the oscillator driver is turned

off. The I/O ports maintain the status they had before

the SLEEP instruction was executed (driving high, low,

or hi-impedance).

For the lowest current consumption in SLEEP mode,

place all I/O pins at either VDD or VSS, with no external

circuitry drawing current from the I/O pins, and disable

external clocks. I/O pins that are hi-impedance inputs

should be pulled high or low externally to avoid switch-

ing currents caused by floating inputs. The T0CKI input

should also be at VDD or VSS. The contribution from

on-chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR pin low.

6.11.2

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

External RESET input on MCLR pin.

WDT wake-up (if WDT was enabled).

Interrupt from RB0/INT pin, RB port change, or

data EEPROM write complete.

Peripherals cannot generate interrupts during SLEEP,

since no on-chip Q clocks are present.

The first event (MCLR Reset) will cause a device

RESET. The two latter events are considered a contin-

uation of program execution. The TO and PD bits can

be used to determine the cause of a device RESET.

The PD bit, which is set on power-up, is cleared when

SLEEP is invoked. The TO bit is cleared if a WDT

time-out occurred (and caused wake-up).

While the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEP instruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases

where the

execution of the instruction following SLEEP

is not

desirable, the user should have a NOP after the

SLEEP

instruction.

FIGURE 6-12:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC+1

PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC+2

Note

XT, HS, or LP oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.

GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

CLKOUT is not available in these osc modes, but shown here for timing reference.

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