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INTEDG датащи(PDF) 290 Page - Microchip Technology |
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INTEDG датащи(HTML) 290 Page - Microchip Technology |
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290 / 478 page ![]() PIC16(L)F1946/47 DS41414D-page 290 2010-2012 Microchip Technology Inc. 24.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator avail- able for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 24-6). When a write occurs to SSPxBUF, the Baud Rate Gen- erator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal “Reload” in Figure 24-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSPx is being operated in. Table 24-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 24-1: FIGURE 24-40: BAUD RATE GENERATOR BLOCK DIAGRAM TABLE 24-4: MSSPx CLOCK RATE W/BRG FCLOCK FOSC SSPxADD 1 + 4 ------------------------------------------------- = Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. SSPM<3:0> BRG Down Counter SSPxCLK FOSC/2 SSPxADD<7:0> SSPM<3:0> SCLx Reload Control Reload |
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