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INTEDG датащи(PDF) 287 Page - Microchip Technology

номер детали INTEDG
подробное описание детали  64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology
PDF  478 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

INTEDG датащи(HTML) 287 Page - Microchip Technology

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 2010-2012 Microchip Technology Inc.
DS41414D-page 287
PIC16(L)F1946/47
24.6.13.2
Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a)
A low level is sampled on SDAx when SCLx
goes from low level to high level.
b)
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDAx and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 24-35).
If SDAx is sampled high, the BRG is reloaded and
begins counting. If SDAx goes from high-to-low before
the BRG times out, no bus collision occurs because no
two masters can assert SDAx at exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition, see Figure 24-36.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 24-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 24-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
Cleared by software
’0’
’0’
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
Interrupt cleared
by software
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
TBRG
TBRG
’0’



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