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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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INTEDG датащи(PDF) 275 Page - Microchip Technology |
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INTEDG датащи(HTML) 275 Page - Microchip Technology |
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275 / 478 page  2010-2012 Microchip Technology Inc. DS41414D-page 275 PIC16(L)F1946/47 24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 24-25). FIGURE 24-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION 24.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. SDAx SCLx SCLx deasserted but slave holds DX ‚ – 1 DX BRG SCLx is sampled high, reload takes place and BRG starts its count 03h 02h 01h 00h (hold off) 03h 02h Reload BRG Value SCLx low (clock arbitration) SCLx allowed to transition high BRG decrements on Q2 and Q4 cycles Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. |
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