INTEDG datasheet(272/478 Pages) MICROCHIP

272 / 478 page

PIC16(L)F1946/47

DS41414D-page 272

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24.5.6 CLOCK STRETCHING

Clock stretching occurs when a device on the bus

holds the SCLx line low effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle data or prepare a response for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCLx.

The CKP bit of the SSPxCON1 register is used to con-

trol stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCLx line to go

low and then hold it. Setting CKP will release SCLx

and allow more communication.

24.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSPxSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPxBUF with data to

transfer to the master. If the SEN bit of SSPxCON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

24.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the

SCLx is stretched without CKP being cleared. SCLx is

released immediately after a write to SSPxADD.

24.5.6.3 Byte NACKing

When AHEN bit of SSPxCON3 is set; CKP is cleared

by hardware after the 8th falling edge of SCLx for a

received matching address byte. When DHEN bit of

SSPxCON3 is set; CKP is cleared after the 8th falling

edge of SCLx for received data.

Stretching after the 8th falling edge of SCLx allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

24.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCLx line to go low and then hold it. However,

clearing the CKP bit will not assert the SCLx output

low until the SCLx output is already sampled low.

Therefore, the CKP bit will not assert the SCLx line

until an external I2C master device has already

asserted the SCLx line. The SCLx output will remain

low until the CKP bit is set and all other devices on the

I2C bus have released SCLx. This ensures that a write

to the CKP bit will not violate the minimum high time

requirement for SCLx (see Figure 24-22).

FIGURE 24-23:

CLOCK SYNCHRONIZATION TIMING

Note 1:

The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock, clear CKP, if

SSPxBUF was read before the 9th falling

edge of SCLx.

Previous versions of the module did not

stretch the clock for a transmission if

SSPxBUF was loaded before the 9th fall-

ing edge of SCLx. It is now always cleared

for read requests.

Note:

Previous versions of the module did not

stretch the clock if the second address byte

did not match.

SDAx

SCLx

DX ‚

– 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON1

CKP

Master device

releases clock

Master device

asserts clock

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