INTEDG datasheet(259/478 Pages) MICROCHIP

259 / 478 page

 2010-2012 Microchip Technology Inc.

DS41414D-page 259

PIC16(L)F1946/47

24.5.2 SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPxSTAT

is set. The BOEN bit of the SSPxCON3 register modi-

fies this operation. For more information see

An MSSPx interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by

software.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See Section 24.2.3 “SPI

Master Mode” for more detail.

24.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSPx module configured as an I2C Slave in

7-bit Addressing mode. Figure 24-13 and Figure 24-14

are used as visual references for this description.

This is a step by step process of what typically must

be done to accomplish I2C communication.

Start bit detected.

S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

Matching address with R/W bit clear is received.

The slave pulls SDAx low sending an ACK to the

master, and sets SSPxIF bit.

Software clears the SSPxIF bit.

Software

reads

received

address

from

SSPxBUF clearing the BF flag.

If SEN = 1; Slave software sets CKP bit to

release the SCLx line.

The master clocks out a data byte.

Slave drives SDAx low sending an ACK to the

master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from

SSPxBUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes idle.

24.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCLx. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

This list describes the steps that need to be taken by

slave software to use these options for I2C communi-

cation. Figure 24-15 displays a module using both

address and data holding. Figure 24-16 includes the

operation with the SEN bit of the SSPxCON2 register

set.

S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

Matching address with R/W bit clear is clocked

in. SSPxIF is set and CKP cleared after the 8th

falling edge of SCLx.

Slave clears the SSPxIF.

Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF

was after or before the ACK.

Slave reads the address value from SSPxBUF,

clearing the BF flag.

Slave sets ACK value clocked out to the master

by setting ACKDT.

Slave releases the clock by setting CKP.

SSPxIF is set after an ACK, not after a NACK.

If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPxIF.

11. SSPxIF set and CKP cleared after 8th falling

edge of SCLx for a received data byte.

12. Slave looks at ACKTIM bit of SSPxCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

Note:

SSPxIF is still set after the 9th falling edge of

SCLx even if there is no clock stretching and

BF has been cleared. Only if NACK is sent

to Master is SSPxIF not set

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