INTEDG datasheet(256/478 Pages) MICROCHIP

256 / 478 page

PIC16(L)F1946/47

DS41414D-page 256

 2010-2012 Microchip Technology Inc.

24.4.4 SDAX HOLD TIME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the

time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns mini-

mum hold time and may help on buses with large

capacitance.

TABLE 24-2:

I2C BUS TERMS

TERM

Description

Transmitter

The device which shifts data out

onto the bus.

Receiver

The device which shifts data in

from the bus.

Master

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave

The device addressed by the mas-

ter.

Multi-master

A bus with more than one device

that can initiate data transfers.

Arbitration

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDAx and SCLx lines are

high.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPxADD.

Write Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCLx low to stall communication.

Bus Collision

Any time the SDAx line is sampled

low by the module while it is out-

putting and expected high state.

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