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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LMP90100MHE/NOPB датащи(PDF) 39 Page - Texas Instruments |
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LMP90100MHE/NOPB датащи(HTML) 39 Page - Texas Instruments |
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39 / 69 page  CSB SCLK MSB 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n LSB INST2 SDI MSB SDO/ DRDYB Data Byte (s) DRDYB is driving the pin SDO is driving the pin LSB 1/fSCLK tCL tCH CSB SCLK MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n LSB INST2 SDI MSB SDO/ DRDYB Data Byte (s) DRDYB is driving the pin SDO is driving the pin LSB 1/fSCLK tCL tCH LMP90100 www.ti.com SNAS510P – JANUARY 2011 – REVISED MARCH 2013 Figure 56. Timing Protocol for DrdybCase1 DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03 SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control register. In this case, DRDYB will drive the pin unless the device is reading data, independent of the state of CSB. SDO will drive the pin when CSB is asserted and the device is reading data. With this scheme, one can use SDO/DRDYB as a true interrupt source, independent of the state of CSB. But this scheme can only be used when the LMP900xx is the only device connected to the master's SPI bus because the SDO/DRDYB pin will be DRDYB even when CSB is deasserted. The timing protocol for this case can be seen in Figure 57. When drdyb asserts, assert CSB to start the SPI transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers. Figure 57. Timing Protocol for DrdybCase2 Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: LMP90100 |
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