Datasheet

Revision History

Revision

Revision Date

Description

0.55

Sept. 1999

Initial release.

0.6

Nov. 1999

• Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect

correct signal transitions.

• Removed “10BASE-T Error Detection and Reporting” section since the

82562 does not do 10BASE-T error reporting.

• Updated bit 13 of Table 3 “Register 16 (10 Hexadecimal): PLC Status, Con-

trol and Address Data” to reflect correct values.

1.0

May 2000

Advance Information Datasheet release (Intel Secret).

• Modified Table 1 “82562ET Hardware Configuration” to add one row for

XOR Tree and include column for comments.

• Updated the descrition of the Activity LED signal in Section 3.6, “LED

Pins”.

• Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to

Table 1 “82562ET Hardware Configuration”.

• Updated Section 6.0, “Electrical and Timing Specifications”.

• Replaced diagrams in Section 7.1, “Package Information”.

1.1

June 2000

Advance Information Datasheet release (Intel Confidential).

• On cover page, replaced Boundary Scan Support with XOR tree mode

support. Added bullet for LAN Connect I/F.

• Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but

replaced EM with ET in diagram.

• Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”.

• Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0.

1.2

Oct 2001

Removed confidential status.

• Removed sections: “Physical Layer Interface Functionality” and “Platform

LAN Connect”.

• Changed “Electrical and Timing Specifications” section to “Voltage and

Temperature Specifications” and removed timing specifications.

1.3

March 2003

• Added product ordering code in Section 1.0.

1.4

Nov 2006

• Corrected the TESTEN signal description.

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