Data Sheet

ADF4159

Rev. B | Page 21 of 36

DEVIATION REGISTER (R5) MAP

When Bits DB[2:0] are set to 101, the on-chip deviation register

(Register R5) is programmed (see Figure 30).

Reserved Bit

The reserved bit must be set to 0 for normal operation.

When Bit DB29 is set to 0, the clock divider clock is used to

is used to clock the ramp.

Parabolic Ramp

When Bit DB28 is set to 1, the parabolic ramp is enabled. When

Bit DB28 is set to 0, the parabolic ramp is disabled. For more

information, see the Parabolic (Nonlinear) Ramp Mode section.

Interrupt

Bits DB[27:26] determine which type of interrupt is used. This

feature is used for reading back the INT and FRAC value of a

pin triggers the interrupt). From the INT and FRAC bits, the

frequency can be obtained. After readback, the sweep can continue

or stop at the readback frequency. For more information, see the

Interrupt Modes and Frequency Readback section.

FSK Ramp Enable

When Bit DB25 is set to 1, the FSK ramp is enabled. When

Bit DB25 is set to 0, the FSK ramp is disabled.

Dual Ramp Enable

When Bit DB24 is set to 1, the second ramp is enabled. When

Bit DB24 is set to 0, the second ramp is disabled.

Deviation Select

When Bit DB23 is set to 0, the first deviation word is selected.

When Bit DB23 is set to 1, the second deviation word is selected.

4-Bit Deviation Offset Word

Bits DB[22:19] determine the deviation offset word. The devia-

tion offset word affects the deviation resolution.

16-Bit Deviation Word

Bits DB[18:3] determine the signed deviation word. The

deviation word defines the deviation step.

16-BIT DEVIATION WORD

CONTROL

BITS

0

0

0

0

0

TR1

I2

I1

DS1

DO4 DO3 DO2 DO1

D16

D15 D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

C3(1) C2(0) C1(1)

I2

I1

INTERRUPT

0

0

INTERRUPT OFF

1

1

D16

D15

...

...

...

...

...

...

...

...

...

...

...

...

D2

D1

DEVIATION WORD

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

1

1

1

1

– 1

1

1

1

0

– 2

1

1

0

1

– 3

1

0

0

0

–32,768

D4

D3

D1

D2

4-BIT DEVIATION

OFFSET WORD

0

1

0

1

DO4

DO3

DO2

DO1

DEV OFFSET WORD

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

.

.

.

.

.

.

.

.

.

.

1

1

0

1

7

1

1

1

0

0

0

0

0

8

9

DS1

DEV SEL

0

DEV WORD 1

1

DEV WORD 2

0

DUAL RAMP

0

DISABLED

1

ENABLED

0

0

DISABLED

1

ENABLED

0

FSK RAMP

0

DISABLED

1

ENABLED

0

PARABOLIC RAMP

0

DISABLED

1

ENABLED

0

CLK DIV

1

TXDATA

0

1

1

1

32,767

.

.

.

.

.

.

.

.

.

.

LOAD CHANNEL CONTINUE SWEEP

NOT USED

LOAD CHANNEL STOP SWEEP

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Figure 30. Deviation Register (R5) Map