ADAS3023

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1 to 4

IN0 to IN3

AI

Input Channel 0 to Input Channel 3.

6 to 9

IN4 to IN7

AI

Input Channel 4 to Input Channel 7.

5, 14, 23,

24, 29,

30, 40

AGND

P

Analog Ground. Connect AGND to the system analog ground plane.

10

COM

AI

IN0 to IN7 Common Channel Input. Input Channel IN0 to Input Channel IN7 are referenced to a common

point. The maximum voltage on this pin is ±10.24 V for all PGIA gains.

11

CS

Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use the CS pin when

sharing the serial bus. For a dedicated and simplified ADAS3023 serial interface, tie CS to DGND or CNV.

12

DIN

DI

Data Input. DIN is the serial data input for writing the 16-bit configuration (CFG) word that is clocked

into the device on the SCK rising edges. The CFG is an internal register that is updated on the rising edge

of the next end of a conversion pulse, which coincides with the falling edge of BUSY/SDO2. The CFG

register is written into the device on the first 16 clocks after conversion. To avoid corrupting a conversion

due to digital activity on the serial bus, do not write data during a conversion.

13

RESET

DI

Asynchronous Reset. A low-to-high transition resets the ADAS3023. The current conversion, if active, is

aborted and the CFG register is reset to the default state.

15

PD

DI

Power-Down. A low-to-high transition powers down the ADAS3023, minimizing the device operating

current. Note that PD must be held high until the user is ready to power on the device. After powering

on the device, the user must wait 100 ms until the reference is enabled and then wait for the completion

of one dummy conversion before the device is ready to convert. Note that the RESET pin remains low for

100 ns after the release of PD. See the Power-Down Mode section for more information.

16

SCK

DI

Serial Clock Input. The DIN and SDO data sent to and from the ADAS3023 are synchronized with SCK.

17

VIO

P

Digital Interface Supply. Nominally, it is recommended that VIO be at the same voltage as the supply of

the host interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.

18

SDO

DO

Serial Data Output. The conversion result is output on this pin and synchronized to the SCK falling

edges. The conversion results are presented on this pin in twos complement format.

19

BUSY/SDO2

DO

Busy/Serial Data Output 2. The converter busy signal is always output on the BUSY/SDO2 pin when CS is

logic high. If SDO2 is enabled when CS is brought low after the EOC, the SDO outputs the data. The

conversion result is output on this pin and synchronized to the SCK falling edges. The conversion results

are presented on this pin in twos complement format.

20

CNV

DI

Convert Input. A conversion is initiated on the rising edge of the CNV pin.

21, 22

DGND

P

Digital Ground. Connect DGND to the system digital ground plane.

25

DCAP

P

Internal 2.5 V Digital Regulator Output. Decouple DCAP, an internally regulated output, using a 10 μF

and a 0.1 μF local capacitor.

26

ACAP

P

Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and to all

of the supporting analog circuits, except for the internal reference. Decouple this internally regulated

output (ACAP) using a 10 μF capacitor and a 0.1 μF local capacitor.

1

IN0

2

IN1

3

IN2

4

IN3

5

AGND

6

IN4

7

IN5

8

IN6

9

IN7

10

COM

23 AGND

24 AGND

25 DCAP

26 ACAP

27 DVDD

28 AVDD

29 AGND

30 AGND

22 DGND

21 DGND

NOTES

1. CONNECT THE EXPOSED PAD TO VSSH.

ADAS3023

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Rev. 0 | Page 10 of 32