DSPB56374AFC datasheet(4/64 Pages) FREESCALE

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DSP56374 Data Sheet, Rev. 4.2

Features

Freescale Semiconductor

•

Six-channel DMA controller

•

Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL

feedback multiplier (2 or 4), Output divide factor (1, 2, or 4) and a power-saving clock divider

(2i: i = 0 to 7) to reduce clock noise

•

Internal address tracing support and OnCE for Hardware/Software debugging

•

JTAG port, supporting boundary scan, compliant to IEEE 1149.1

•

Very low-power CMOS design, fully static design with operating frequencies down to DC

•

STOP and WAIT low-power standby modes

2.2

On-chip Memory Configuration

•

6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM

•

6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM

•

20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism

•

6Kx24 Bit Program RAM.

•

Various memory switches are available. See memory table below.

2.3

Peripheral

Modules

•

Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master

or slave. I2S, Sony, AC97, network, and other programmable protocols.

•

Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins,

master or slave. I2S, Sony, AC97, network and other programmable protocols. Note: Available in

the 80-pin package only.

•

Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16, and

24-bit words. Three noise reduction filter modes.

•

Triple Timer module (TEC)

•

Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be

configured as GPIO on the 80 pin package and 20 pins on the 52 pin package.

Table 1. DSP56374 Memory Switch Configurations

Bit Settings

Memory Sizes (24-bit words)

MSW1

MSW0

Prog

RAM

X Data

RAM

Y Data

RAM

Prog

ROM

X Data

ROM

Y Data

ROM

20K

10K

20K

10K

20K

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