MPIC2131

3

Motorola Power Products Division Advanced Data

RECOMMENDED OPERATING CONDITIONS

The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended condi-

tions. The VS offset rating is tested with all supplies biased at 15 V differential.

High Side Floating Supply Absolute Voltage

VB1,2,3

VS1,2,3+10

VS1,2,3+20

V

High Side Floating Supply Offset Voltage

VS1,2,3

Note 1

VSO+600

V

High Side Floating Output Voltage

VHO1,2,3

VS1,2,3

VB1,2,3

V

Fixed Supply Voltage

VCC

10

20

V

Low Side Output Voltage

VLO1,2,3

0

VCC

V

Low Side Driver Return

VSS

–5

5

V

Logic Input Voltage (HIN–, LIN–, FLT–CLR, SD & ITRIP)

VIN

VSS

5

V

Fault Output Voltage

FAULT–

VSS

VCC

V

Ambient Temperature

TA

–40

125

°C

Note 1: Logic operational for VS of –5 V to +600 V. Logic state held for VS of –5 V to –VBS.

Characteristic

Symbol

Min

Typ

Max

Unit

STATIC ELECTRICAL CHARACTERISTICS

VBIAS (VCC, VBS1,2,3) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are

applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to COM and VSO1,2,3 and are applicable to

the respective output leads: HO1,2,3 or LO1,2,3.

Logic “0” Input Voltage (OUT = LO)

VIH

2.2

–

–

V

Logic “1” Input Voltage (OUT = HI)

VIL

–

–

0.8

V

Logic “0” Fault Clear Input Voltage

VFCLR,IH

2.2

–

–

V

Logic “1” Fault Clear Input Voltage

VFCLR,IL

–

–

0.8

V

SD Input Positive Going Threshold

VSD,TH+

–

1.8

–

V

SD Input Negative Going Threshold

VSD,TH–

–

1.5

–

V

ITRIP Input Positive Going Threshold

VIT,TH+

–

485

–

mV

ITRIP Input Negative Going Threshold

VIT,TH–

–

400

–

mV

High Level Output Voltage, VBIAS–VO @ VIN = 0 V, IO = 0 A

VOH

–

–

100

mV

Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A

VOL

–

–

100

mV

Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V

ILK

–

–

50

µA

Quiescent VBS Supply Current @ VIN = 0 V or 5 V

IQBS

–

30

–

µA

Quiescent VCC Supply Current @ VIN = 0 V or 5 V

IQCC

–

3.0

–

mA

Logic “1” Input Bias Current (OUT = HI) @ VIN = 0 V

IIN+

–

190

–

µA

Logic “0” Input Bias Current (OUT = LO) @ VIN = 5 V

IIN–

–

100

–

µA

“High” ITRIP Bias Current @ ITRIP = 5 V

ITRIP+

–

60

–

µA

“Low” ITRIP Bias Current @ ITRIP = 0 V

ITRIP–

–

–

50

nA

Logic “1” Fault Clear Bias Current @ FLT–CLR = 0 V

IFCLR+

–

190

–

µA

Logic “0” Fault Clear Bias Current @ FLT–CLR = 5 V

IFCLR–

–

100

–

µA

Logic “1” Shut Down Bias Current @ SD = 5 V

ISD+

–

60

–

µA

Logic “0” Shut Down Bias Current @ SD = 5 V

ISD–

–

–

150

nA

VBS Supply Undervoltage Positive Going Threshold

VBSUV+

–

8.6

–

V

VBS Supply Undervoltage Negative Going Threshold

VBSUV–

–

8.2

–

V

VCC Supply Undervoltage Positive Going Threshold

VCCUV+

–

9.0

–

V

VCC Supply Undervoltage Negative Going Threshold

VCCUV–

–

8.7

–

V

FAULT – Low On Resistance

Ron,FLT

–

55

–

Ω

Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW ≤ 10 µs

IO+

200

250

–

mA

Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW ≤ 10 µs

IO–

420

500

–

mA