ADM1065ASUZ datasheet(21/28 Pages) AD

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ADM1065

Rev. D | Page 21 of 28

The device also has several identification registers (read-only)

that can be read across the SMBus. Table 10 lists these registers

with their values and functions.

Table 10. Identification Register Values and Functions

Name

Address

Value

Function

MANID

0xF4

0x41

Manufacturer ID for Analog

Devices

REVID

0xF5

0x02

Silicon revision

MARK1

0xF6

0x00

Software brand

MARK2

0xF7

0x00

Software brand

General SMBus Timing

Figure 26, Figure 27, and Figure 28 are timing diagrams for

general read and write operations using the SMBus. The SMBus

specification defines specific conditions for different types of

read and write operations, which are discussed in the Write

Operations and Read Operations sections.

The general SMBus protocol operates as follows:

Step 1

The master initiates data transfer by establishing a start condition,

defined as a high-to-low transition on the serial data-line SDA,

while the serial clock-line SCL remains high. This indicates that

a data stream follows. All slave peripherals connected to the serial

bus respond to the start condition and shift in the next eight bits,

consisting of a 7-bit slave address (MSB first) plus an R/W bit. This

bit determines the direction of the data transfer, that is, whether

data is written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowledge

bit (ACK), and holding it low during the high period of this

clock pulse.

All other devices on the bus remain idle while the selected device

waits for data to be read from or written to it. If the R/W bit is a 0,

the master writes to the slave device. If the R/W bit is a 1, the

master reads from the slave device.

Step 2

Data is sent over the serial bus in sequences of nine clock pulses:

eight bits of data followed by an acknowledge bit from the slave

device. Data transitions on the data line must occur during the

low period of the clock signal and remain stable during the high

period because a low-to-high transition when the clock is high

could be interpreted as a stop signal. If the operation is a write

operation, the first data byte after the slave address is a command

byte. This command byte tells the slave device what to expect next.

It may be an instruction telling the slave device to expect a block

write, or it may be a register address that tells the slave where

subsequent data is to be written. Because data can flow in only

one direction, as defined by the R/W bit, sending a command

to a slave device during a read operation is not possible. Before

a read operation, it may be necessary to perform a write operation

to tell the slave what sort of read operation to expect and the

address from which data is to be read.

Step 3

When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line high

during the 10th clock pulse to assert a stop condition. In read

mode, the master device releases the SDA line during the low

period before the ninth clock pulse, but the slave device does

not pull it low. This is known as a no acknowledge. The master

then takes the data line low during the low period before the

10th clock pulse and then high during the 10th clock pulse to

assert a stop condition.

START BY

MASTER

ACK. BY

SLAVE

ACK. BY

SLAVE

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME 2

COMMAND CODE

FRAME 1

SLAVE ADDRESS

FRAME N

DATA BYTE

FRAME 3

DATA BYTE

SCL

SDA

R/W

STOP

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

Figure 26. General SMBus Write Timing Diagram

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