MPC993

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 3

4

Applications Information

The MPC993 is a single switch circuit. The device

continuously monitors the two input signals to identify faulty

reference clocks. A clock is considered faulty if it has been

stuck LOW or HIGH for 3 consecutive feedback clock edges

(rising or falling). Upon identifying a faulty reference clock, an

input bad flag (Inp0bad or Inp1bad) corresponding to the

faulty clock will be set. If the PLL was currently locked to the

input signal that goes bad, the MPC993 will automatically

switch to the other clock provided it is operational. The input

bad flags will remain set until an Alarm_Reset is asserted.

The Alarm_Reset input is an active LOW input that will reset

the input bad flag(s). Note that the Alarm_Reset is one

shotted, thus if upon clearing the input bad flags the inputs

are still bad the flags will be reset without the Alarm_Reset

pin being negated.

If both of the input signals go bad simultaneously the

MPC993 PLL will lose lock and the VCO will drift to an

indeterminate frequency. Once the MPC993 switches from a

bad clock it will continue to use the new clock until the

Alarm_Reset pin is asserted. The device will not switch back

to a “repaired” bad input clock until the Alarm_Reset is

asserted. Asserting the Alarm_Reset pin forces the

Clk_Selected output to match the Sel_Clk input. Users

identify their primary clock via the Sel_Clk input. If not faulty

the MPC993 will always lock to this clock source in the

normal mode of operation. The only time clock Clk_Selected

does not equal Sel_Clk is when the device is in automatic

switch mode and the primary clock source is faulty. In this

condition the MPC993 will have switched to the secondary

clock and Clk_Selected will be in the opposite state as

Sel_Clk. Note that when in manual override (Man_Override

input is asserted) Clk_Selected will always equal Sel_Clk

regardless of the condition of the input bad flags.

Upon detection and switch from a “bad” input to a “good”

one, the internal PLL of the MPC993 will ensure a smooth

phase transition from the original to the new reference clock

source. The magnitudes of the disturbances seen in the

output clocks are detailed in the AC tables of this data sheet.

The two datasheet specifications are the maximum phase

error deviation and the rate of change of the output periods

during a reference clock switch. The maximum phase error

deviation describes the change in the input/output phase

difference caused by a switch between two out–of–phase

references. The rate of change periods describes the

behavior of the output signals from the MPC993 as it requires

phase–lock to the new reference source. Two different

conditions are specified, one for a maximum phase deviation

of the two clock sources of

≤±400ps and the other for phase

deviations of

≤±π. Under these conditions the MPC993 will be

guaranteed to take the “shortest path” to regain phase lock.

That is for a phase difference of –300ps, the output phase will

slew 300ps to align to the new phase as opposed to travelling

one clock period minus 300ps in the other direction. This

guarantee will ensure phase coherency in a clocking scheme

in which multiple MPC993’s are synchronized in a clock tree

and a subset of the devices under go a dynamic switch. Note

if the phase of the two input clock sources differs by more

than

±π the direction of phase lock cannot be guaranteed.

To calculate the overall uncertainty between any clocks

from multiple MPC993’s the following procedure should be

followed. Assuming that the reference clocks to the multiple

MPC993’s are exactly in phase, the total uncertainty will be

the combination of the static phase offset uncertainty

between the reference and feedback clocks, plus the

uncertainty between the feedback clock and the other clock

outputs, plus the jitter between the reference clock and

feedback clock inputs to the PLL. Based on the preliminary

data sheet specifications on this data sheet the total

uncertainty between CPU clocks would be 300ps + 50ps +

200ps or 550ps. The numbers used to derive this are the

Tpd, Output Skew and I/O jitter numbers respectively. Any

uncertainty in the phase of the reference clocks between the

different MPC993’s will add directly to this calculated

uncertainty.

During a dynamic switch the part to part skew between

two devices may be increased for a short period of time. In

the condition that only a subset of a number of parallel

MPC993’s under go a dynamic switch an additional

component will need to be added to the part to part skew of

the device during this transient event. If the two reference

clocks are 400ps out of phase a dynamic switch of an

MPC993 will lead to an instantaneous change of the input

phase by 400ps without a corresponding change in the

output phase due to the limited bandwidth of the PLL. As a

result the delay through a device under going the above

described switch will change by 400ps until the PLL has an

opportunity to slew to its new phase. This transient timing

issue should be considered when analyzing the overall skew

budget of a system.

The MPC993 inputs are not designed for “hot insertion”

applications when the device is used in a PECL environment.

In an ECL environment the reference clock inputs to the

device are hot insertion compatible. However in a PECL

environment a powered down receiver will present a low

impedance connection to ground to a powered up driver. To

make the MPC993 hot insertion compatible in a PECL

environment series resistance needs to be added in front of

the input reference clock pins to limit the current in the above

mentioned case. For a 3.3V PECL environment a 100

Ω

series resistor will be sufficient to limit the current to

acceptable levels for both the driver and the receiver. A 100

Ω

series resistor on the reference clock inputs will have minimal

impact on the rise and fall times of the input signals.