MPC992

MOTOROLA

TIMING SOLUTIONS

BR1333 — REV 5

2

Qb1

Qb2

Qa1

Qa1

Qa0

GNDA

VCCA

VCCI

Qb0

Qb1

Qb2

PLL_EN

GNDI

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

345678

24

23

22

21

20

19

18

17

16

MPC992

Reset

Qa0

Qb0

FUNCTION TABLE 1

FSEL0

FSEL1

Qa

Qb

Feedback

Ratio

0

0

1

1

0

1

0

1

VCO/4

VCO/2

VCO/4

VCO/2

VCO/6

VCO/4

VCO/10

VCO/6

VCO/24

VCO/16

VCO/40

VCO/24

3:2

2:1

5:2

3:1

INPUT vs OUTPUT FREQUENCY

FSEL0

FSEL1

Qa

Qb

Int Feedback

0

0

1

1

0

1

0

1

6 (fref)

8 (fref)

10 (fref)

12 (fref)

4 (fref)

4 (fref)

4 (fref)

4 (fref)

fref

fref

fref

fref

FUNCTION TABLE 2

Control Signal

Logic ‘0’

Logic ‘1’

Reset

Outputs Enabled

Outputs Disabled

XTAL_SEL

PECL REF

XTAL REF

PLL_EN

Disabled

Enabled

VCO_SEL

High Frequency

Low Frequency

PIN DESCRIPTION

Pin Name

Function

VCO_SEL

VCO range select pin (Int Pullup)

PLL_EN

PLL bypass select pin (Int Pullup)

XTAL_SEL

Input reference source select pin (Int Pullup)

XTAL1:2

Crystal interface pins for the internal oscillator

PECL_CLK

True PECL reference clock input (Int Pulldown)

PECL_CLK

Compliment PECL reference clock input

(Int Pullup)

FSELn

Internal divider select pins (Int Pullup)

RESET

Internal flip–flop reset, true outputs go LOW

(Int Pulldown)