MPC2104P datasheet(13/16 Pages) MOTOROLA

номер детали	MPC2104P

подробное описание детали	256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

PDF	16 Pages

Scroll/Zoom	100%

производитель	MOTOROLA [Motorola, Inc]

домашняя страница	http://www.freescale.com

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13 / 16 page

MPC2104P

•MPC2105P

MOTOROLA FAST SRAM

TAG RAM MATCH CYCLE

Sb l

Tag RAM

Parameter

Symbol

Min

Max

Unit

Clock High Write to MATCH Invalid

tKHML

—

Clock High Read to MATCH Valid

tKHMV

—

Address Valid to MATCH Valid

tAVMV

—

MATCH Valid Hold from Address Change

tAXMX

—

TG Low to MATCH Invalid

tGLML

—

TG High to MATCH Valid

tGHMX

—

TAG RAM RESET (TCLR) CYCLE

Sb l

Tag RAM

Parameter

Symbol

Min

Max

Unit

TCLR Setup Time

tSTC

—

TCLR Hold Time

tHTC

—

Status Bit Reset Time

tSRST

—

Status Bit Hold from TCLR Low

tSHRS

—

TCLR Low to MATCH Invalid

tRSML

—

TCLR High to MATCH Valid

tRSMV

—

100

TCLR Low to TAG High–Z

tRSQZ

—

TCLR High to TAG Active

tRSQX

—

100

STANDBY Setup to TCLR Low

tPDSR

—

TCLR High to TWE Low

tRHWX

—

OUTPUT

Z0 = 50 Ω

Ω

VL = 1.5 V

(a)

(b)

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

TIMING LIMITS

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time. On the other hand, responses

from the memory are specified from the de-

vice point of view. Thus, the access time is

shown as a maximum since the device never

provides data later than that time.

Figure 1. Test Loads

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