WM8903 datasheet(97/178 Pages) WOLFSON

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Production Data

WM8903

PD, Rev 4.5, June 2012

CLK_SYS CONTROL

The CLK_SRC_SEL bit is used to select the source for CLK_SYS. The source may be either the

MCLK input or the FLL output. The selected source may be adjusted by the MCLKDIV2 divider to

generate CLK_SYS. These register fields are described in Table 61. See “Frequency Locked Loop

(FLL)” for more details of the Frequency Locked Loop clock generator.

The CLK_SYS signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 1 for normal

operation with MCLK applied. This bit should be set to 0 when reconfiguring clock sources. It is not

recommended to change CLK_SRC_SEL while the CLK_SYS_ENA bit is set.

The following operating frequency limits must be observed when configuring CLK_SYS. Failure to

observe these limits will result in degraded noise performance and/or incorrect ADC/DAC

functionality.



If DAC_OSR = 0 then CLK_SYS

 3MHz



If DAC_OSR = 1 then CLK_SYS

 6MHz

For DAC operation up to 48kHz sample rate, the following CLK_SYS limits are applicable. These

conditions are applicable whenever DACL_ENA = 1 or DACR_ENA = 1.

Note that the ADC operation limits must also be observed if either ADC is enabled. See “Digital-to-

Analogue Converter (DAC)” for definitions of DAC_MONO and DAC_OSR.



If DAC_MONO = 0 and DAC_OSR = 0, then CLK_SYS

 128 x fs



If DAC_MONO = 0 and DAC_OSR = 1, then CLK_SYS

 256 x fs



If DAC_MONO = 1 and DAC_OSR = 0, then CLK_SYS

 64 x fs



If DAC_MONO = 1 and DAC_OSR = 1, then CLK_SYS

 128 x fs

For ADC operation up to 48kHz sample rate, the following CLK_SYS limits are applicable. These

conditions are applicable whenever ADCL_ENA = 1 or ADCR_ENA = 1.

Note that the DAC operation limits must also be observed if either DAC is enabled. See “Analogue-to-

Digital Converter (ADC)” for the definition of ADC_OSR.



If ADC_OSR = 0, then CLK_SYS

 128 x fs



If ADC_OSR = 1, then CLK_SYS

 256 x fs

Further requirements for 88.2kHz and 96kHz operation are provided later in this section. Note that

simultaneous ADC and DAC operation at 88.2kHz or 96kHz is not possible.

The clocking of the ADC and DAC circuits is derived from CLK_DSP, which is enabled by

CLK_DSP_ENA. (Note that CLK_SYS must also be enabled.)

A 256kHz clock required for the Control Write Sequencer and MICBIAS Current Detect filtering is

derived from CLK_SYS. The 256kHz clock is enabled by WSMD_CLK_ENA.

The slow clock (TOCLK) required for input signal de-bouncing and volume update timeout functions is

derived from the 256kHz clock. The TOCLK clock is enabled by TO_ENA.

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