Preliminary Technical Data

WM8788

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PTD, December 2010, Rev 2.2

13

DIGITAL AUDIO INTERFACE CONTROL

The digital audio interface protocol is selected using the control pins AIFMODE0 and AIFMODE1, as

described in Table 1.

AIFMODE1

AIFMODE0

FORMAT

0

0

16-bit Right-justified

0

1

20-bit Right-justified

0

Z

24-bit Right-justified

1

0

16-bit Left-justified

1

1

20-bit Left-justified

1

Z

24-bit Left-justified

Z

0

16-bit I2S

Z

1

20-bit I2S

Z

Z

24-bit I2S

Table 1 Digital Audio Interface Mode Select

For Slave Mode, set MASTER = 0 and set OSR according to the applicable sample rate.

MASTER

OSR

SAMPLE RATE

0

0

8, 16, 32, 44.1, 48kHz

0

1

88.2, 96kHz

0

Z

176.4, 192kHz

Table 2 Slave Mode Configuration

In Slave Mode, the MCLK and LRCLK inputs must conform to a valid clocking ratio, as noted below.

The LRCLK frequency is the same as the sample rate, fs. MCLK frequencies of 128fs, 192fs, 256fs,

384fs, 512fs and 768fs can be supported, depending on the sample rate.

The BCLK signal is an input to the WM8788 in slave mode. A range of BCLK frequencies can be

supported, provided there are sufficient BCLK cycles for the selected data word length. The BCLK

frequency must not be higher than the MCLK frequency, and must not be higher than 12.288MHz.

SAMPLE RATE

MCLK FREQUENCY (MHz)

128fs

192fs

256fs

384fs

512fs

768fs

8kHz

n/a

n/a

2.048

3.072

4.096

6.144

16kHz

n/a

n/a

4.096

6.144

8.192

12.288

32kHz

n/a

n/a

8.192

12.288

16.384

24.576

44.1kHz

n/a

n/a

11.2896

16.9344

22.5792

33.8688

48kHz

n/a

n/a

12.288

18.432

24.576

36.864

88.2kHz

11.2896

16.9344

22.5792

33.8688

n/a

n/a

96kHz

12.288

18.432

24.576

36.864

n/a

n/a

176.4kHz

22.5792

33.8688

n/a

n/a

n/a

n/a

192kHz

24.576

36.864

n/a

n/a

n/a

n/a

Table 3 MCLK Frequency in Slave Mode