AD5263BRUZ200-R7 datasheet(16/28 Pages) AD

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AD5263

Data Sheet

Rev. F | Page 16 of 28

I2C-COMPATIBLE DIGITAL INTERFACE (DIS = 1)

The word format maps in this section use the following abbreviations.

Abbreviation

Description

Start condition.

Stop condition.

Acknowledge.

AD1, AD0

I2C device address bits. Must match with the logic states at Pin AD1 and Pin AD0. Refer to Figure 49.

A1, A0

RDAC channel select.

Software reset wiper (A1, A0) to midscale position.

Shutdown active high; ties wiper (A1, A0) to Terminal B, opens Terminal A, RDAC register contents are not disturbed.

To exit shutdown, the command SD = 0 must be executed for each RDAC (A1, A0).

O1, O2

Data to digital output pins, Pin O1 and Pin O2 in I2C mode, used to drive external logic. The logic high level is

determined by V

L and the logic low level is GND.

Write = 0.

Read = 1.

D7, D6, D5, D4, D3,

D2, D1, D0

Data bits.

Don’t care.

I2C WRITE MODE DATA-WORD FORMAT

AD1

AD0

Slave Address Byte

Instruction Byte

Data Byte

I2C READ MODE DATA-WORD FORMAT

AD1

AD0

Slave Address Byte

Data Byte

SCL

SDA

t10

Figure 42. Detailed I2C Timing Diagram

SCL

START BY

MASTER

ACK BY

AD5263

STOP BY

MASTER

SDA

AD1 AD0 R/W

ACK BY

AD5263

ACK BY

AD5263

FRAME 1

SLAVE ADDRESS BYTE

FRAME 1

INSTRUCTION BYTE

FRAME 1

DATABYTE

Figure 43

. Writing to the RDAC Register

NO ACK

BY MASTER

SCL

SDA

AD1 AD0 R/W

FRAME 1

FRAME 2

START BY

MASTER

ACK BY

AD5263

SLAVE ADDRESS BYTE

RDAC REGISTER

STOP BY

MASTER

Figure 44. Reading Data from a Previously Selected RDAC Register in Write Mode

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