ADIS16445SLASHPCBZ datasheet(11/24 Pages) AD

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Data Sheet

ADIS16445

Rev. A | Page 11 of 24

Burst Read Function

The burst read function enables the user to read all output registers

using one command on the DIN line, 0x3E00. When using this

mode, one can read all of the data in one continuous stream of

bits (no stall time between each register). After the 0x3E00

command, use 12 sequential, 16-bit read commands to complete

the sequence (DIN is “don’t care” after 0x3E00). Figure 13 provides

the burst read sequence of data on each SPI signal. The sequence

starts with writing 0x3E00 to DIN, followed by each output

appear in Figure 12.

GLOB_CMD

SCLK

DIN

DOUT

XGYRO_OUT

DIAG_STAT

TEMP_OUT

Figure 13. Burst Read Sequence

SPI Read Test Sequence

Figure 14 provides a test pattern for testing the SPI communica-

tion. In this pattern, write 0x5600 to the DIN line in a repeating

pattern and raise chip select for at least 9 μs between each 16-bit

sequence. Starting with the second 16-bit sequence, DOUT

produces the contents of the PROD_ID register, 0x403D (see

Table 22).

DOUT = 0100 0000 0011 1101 = 0x403D = 16,445

DIN = 0101 0110 0000 0000 = 0x5600

SCLK

DIN

DOUT

Figure 14. SPI Test Read Pattern DIN = 0x5600, DOUT = 0x403D

DEVICE CONFIGURATION

The control registers in Table 6 provide users with a variety of

configuration options. The SPI provides access to these registers,

one byte at a time, using the bit assignments in Figure 12. Each

and Bits[15:8] represent the upper address. Figure 15 provides

an example of writing 0x04 to Address 0x37 (SMPL_PRD[15:8],

using DIN = 0xB704). This example reduces the sample rate by

a factor of eight (see Table 28).

SCLK

DIN

DIN = 1011 0111 0000 0100 = 0xB704, WRITES 0x04 TO ADDRESS 0x37.

Figure 15. Example SPI Write Sequence

Dual Memory Structure

Writing configuration data to a control register updates its

SRAM contents, which are volatile. After optimizing each

relevant control register setting in a system, set GLOB_CMD[3]

= 1 (DIN = 0xBE08) to back up these settings in nonvolatile

flash memory. The flash backup process requires a valid power

supply level for the entire process time, 75 ms. Table 6 provides

a user register memory map that includes a flash backup

column. A Yes in this column indicates that a register has a

mirror location in flash and, when backed up properly, it

automatically restores itself during startup or after a reset.

Figure 16 provides a diagram of the dual memory structure

used to manage operation and store critical user settings.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 16. SRAM and Flash Memory Diagram

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