AD9119BBCZ datasheet(44/68 Pages) AD

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AD9119/AD9129

Data Sheet

Rev. 0 | Page 44 of 68

Figure 136 shows an example of two AD9119/AD9129 devices

that are synchronized to the same host (that is, FPGA and ASIC).

Note that, when the same resources are used to generate these out-

put signals, synchronization to a single host IC ensures minimum

data and DCI time skew between devices.

Even after FIFO initialization, a phase ambiguity exists between

the read pointers of each device because the read counter of each

device powers up in an arbitrary state. Therefore, the exact instance

when the respective write pointer is set to 4, after the FRAME

signal is asserted, also remains ambiguous. It is possible for the

read pointer of one device to reach its 0 count several clock

cycles before another device (see Figure 134).

Synchronization within a data sample requires insight into the

difference between the read pointers of the master and slave

devices, as well as the ability to vary the delay of the slave device(s)

within the host to compensate for initial offsets between devices.

It is possible to calculate how many data samples the slave device(s)

is offset from the master device for the following reasons:

•

The pipeline delay of each device is the same after FIFO

initialization.

•

The read counter of each device is derived from the same

phase aligned DACCLK source.

•

The state of the read counters of each device is sampled at

the same instance in time via the FRAME signal.

•

The readback value (Register 0x12[6:4]) is normalized to

a data sample (that is, a DACCLK period).

By calculating the difference between the read pointer settings

of the master and slave devices, the user can advance or delay

the data stream of the slave device within the FPGA. Because

this difference can be up to ±4 data samples, the FPGA must

provide this adjustment range for DAC synchronization alone.

Note that additional range must be added to compensate for any

other system delay variation.

In addition to synchronizing to the data sample level, the AD9119/

AD9129 can enable synchronization to the DACCLK level (see

Figure 135). A 1.8 V CMOS output pin, SYNC, can be used to

provide a DACCLK/8 signal. Using the SYNC output from each

DAC, enabled by Register 0x1A, Bit 4 = 1, the user can create

a simple phase detector with an external XOR gate.

DAC 1

SYNC

DAC 2

SYNC

XOR

Figure 135. Example of Synchronization of Two DACs to

±1 DACCLK Accuracy

By adjusting the internal delay (incrementing or decrementing

by one DACCLK cycle with each write to Register 0x1A, Bit 7 or

Bit 6, respectively), the user can align the DACCLKs inside the two

DACs to within ±1 DACCLK cycle, when errors from the external

phase detector, low-pass filter, and delay differences are taken

into account. The existing phase position can be read from

the FIFOs on each DAC to ensure that proper sync is achieved.

This calibration must be performed at each power-up because

the FIFOs can be reset to any of four levels based on the divide-

by-4 output of the clock distribution block (see Figure 133). For

example, a FIFO reset to Level 2 could have an actual FIFO level

of 1.5, 1.75, 2, or 2.25, based on the location of the div-by-4 clock

edge. Adjusting the SYNC signals to align with each other

eliminates this ambiguity.

When the two DACs are aligned, the drift over temperature and

supply voltage of the DACCLK signal of one DAC, relative to

another DAC, is expected to be no more than 450 ps.

The DCO signal is derived from the SYNC signal such that if

the SYNC signal is adjusted by a DACCLK cycle, the DCO

signal must also be adjusted by the same amount.

When all adjustments of the SYNC signal are complete, it is

recommended to disable the SYNC output by programming

spurious signals.

AD9129

MASTER

DACCLK

MATCHED

DELAYS

DCI

ADCLK925

1.4GHz

2.8GHz

COMMON

CLOCK

SOURCE

DCO_x

FPGA

DCI_x

FRM_x

AD9129

SLAVE

DACCLK

DCO_x

DCI_x

FRM_x

0+ dBm

Figure 136. Example of Synchronization of Two DACs to One FPGA

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