Data Sheet

AD5689/AD5687

Rev. 0 | Page 21 of 24

LOAD DAC (HARDWARE LDAC PIN)

The AD5689/AD5687 DACs have double buffered interfaces

consisting of two banks of registers: input registers and DAC

registers. The user can write to any combination of the input

registers. Updates to the DAC register are controlled by

the LDAC pin.

Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC

Instantaneous DAC Updating (LDAC Held Low)

LDAC is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

the DAC register are updated on the rising edge of SYNC, and

then the output begins to change (see Table 14 and Table 15).

Deferred DAC Updating (LDAC Pulsed Low)

LDAC is held high while data is clocked into the input register

using Command 0001. Both DAC outputs are asynchronously

updated by taking LDAC low after SYNC is taken high. The

update then occurs on the falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for a software LDAC mask function,

which allows the address bits to be ignored. A write to the DAC

using Command 0101 loads the 4-bit LDAC mask register (DB3

to DB0). The default setting for each channel is 0; that is, the LDAC

pin works normally. Setting the selected bit to 1 forces the DAC

channel to ignore transitions on the LDAC pin, regardless of

the state of the hardware LDAC pin. This flexibility is useful

in applications where the user wishes to select which channels

respond to the LDAC pin.

The LDAC mask register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 13). Setting an LDAC bit

(DB3, DB0) to 0 for a DAC channel means that the update of

this channel is controlled by the hardware LDAC pin.

Table 13. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits

(DB3, DB0)

LDAC Pin

LDAC Operation

0

1 or 0

Determined by the LDAC pin.

1

X1

DAC channels update and override

the LDAC pin. DAC channels see

the LDAC pin as set to 1.

1

X = don’t care.

Table 14. 24-Bit Input Shift Register Contents for LDAC Operation1

DB23

(MSB)

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB4

DB3

DB2

DB1

DB0

(LSB)

0

0

0

1

X

X

X

X

X

DAC B

0

0

DAC A

Command bits (C3 to C0)

Address bits, don’t care

Don’t care

Setting the LDAC bit to 1 overrides the LDAC pin

1

X = don’t care.

Table 15. Write Commands and LDAC Pin Truth Table1

Command

Description

Hardware LDAC

Pin State

Input Register Contents

DAC Register Contents

0001

Write to Input Register n

(dependent on LDAC)

Data update

No change (no update)

GND2

Data update

Data update

0010

Update DAC Register n with

contents of Input Register n

No change

Updated with input register contents

GND

No change

Updated with input register contents

0011

Write to and update DAC Channel n

Data update

Data update

GND

Data update

Data update

1

A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

(blocked) by the LDAC mask register.

2

When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.

SYNC

SCLK

DAC

REGISTER

INTERFACE

LOGIC

OUTPUT

AMPLIFIER

LDAC

SDO

SDIN

INPUT

REGISTER

16-/12-BIT

DAC