AD5535B

Data Sheet

Rev. A | Page 12 of 16

FUNCTIONAL DESCRIPTION

The AD5535B consists of a 32-channel, 14-bit DAC with 200 V

high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA

package. The output voltage range is programmable via the

REF_IN pin. The output range is 0 V to 50 V when REF_IN =

1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to

the device is through a serial interface operating at clock rates of

up to 30 MHz, which is compatible with DSP and microcontroller

interface standards. A 5-bit address and a 14-bit data-word are

loaded into the AD5535B input register via the serial interface.

The channel address is decoded, and the data-word is converted

into an analog output voltage for this channel.

At power-on, all the DAC registers are loaded with 0s.

DAC SECTION

The architecture of each DAC channel consists of a resistor

string DAC, followed by an output buffer amplifier operating

with a nominal gain of 50. The voltage at the REF_IN pin

provides the reference voltage for the corresponding DAC. The

input coding to the DAC is straight binary, and the ideal DAC

output voltage is given by

14

_

2

50

D

V

V

IN

REF

OUT

×

×

=

where D is the decimal equivalent (0 to 16,383) of the binary

code, which is loaded to the DAC register.

The output buffer amplifier is specified to drive a load of 1 MΩ

and 200 pF. The linear output voltage range for the output amplifier

typically 30 kHz, and is capable of sourcing 550 µA and sinking

2.8 mA. Settling time for a ¼ to ¾ full-scale step change is

typically 60 µs with a load of up to 200 pF.

RESET FUNCTION

The reset function on the AD5535B can be used to reset all

nodes on the device to their power-on reset condition. All the

DACs are loaded with 0s, and all registers are cleared. Take

the RESET pin low to implement the reset function.

SERIAL INTERFACE

The serial interface is controlled by the three following pins:

• SYNC, which is the frame synchronization pin for the serial

interface.

• SCLK, which is the serial clock input that operates at clock

speeds of up to 30 MHz.

upon the falling edge of SCLK.

To update a single DAC channel, a 19-bit data-word is written

to the AD5535B input register.

A4 to A0 Bits

The A4 to A0 bits can address any one of the 32 channels. A4 is

the MSB of the address, while A0 is the LSB.

DB13 to DB0 Bits

The DB13 to DB0 bits are used to write a 14-bit data-word into

the addressed DAC register.

Figure 2 is the timing diagram for a serial write to the

AD5535B. The serial interface works with both a continuous

and a discontinuous serial clock. The first falling edge of SYNC

resets the serial clock counter to ensure that the correct number

of bits are shifted into the serial shift register. Any further edges

on SYNC are ignored until the correct number of bits are

shifted in. After 19 bits are shifted in, the SCLK is ignored. For

another serial transfer to take place, the counter must be reset

by the falling edge of SYNC. The user must allow 200 ns

(minimum) between successive writes.

Figure 15. Serial Data Format

MICROPROCESSOR INTERFACING

AD5535B-to-ADSP-BF527 Interface

The Blackfin® DSP is easily interfaced to the AD5535B without

the need for extra logic. A data transfer is initiated by writing a

word to the TX register after SPORT is enabled. In a write

sequence, data is clocked out on each rising edge of the serial

clock of the DSP and clocked into the AD5535B on the falling

edge of its SCLK. The SPORT can be configured to transmit 19

SCLKs while TFS is low. Figure 16 shows the connection diagram.

Figure 16. AD5535B-to-ADSP-BF527 Interface

A4

A3

A2

A1

A0

DB13 TO DB0

MSB

LSB

ADSP-BF527

SYNC

SPORT_TFS

SCLK

SPORT_TSCK

SDIN

SPORT_DTO

GPIO0

RESET

AD5535B