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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CA16B2CNN датащи(PDF) 22 Page - Agere Systems |
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CA16B2CNN датащи(HTML) 22 Page - Agere Systems |
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22 / 30 page  22 22 Agere Systems Inc. CA16-Type 2.5 Gbits/s DWDM Transponder with Advance Data Sheet 16-Channel 155 Mbits/s Multiplexer/Demultiplexer March 2001 Timing Characteristics (continued) PCLK-to-PICLK Timing After powerup or RESET, the LOCKDET signal will go active, signifying that the PLL has locked to the clock provided on the TXREFCLK input. The FIFO is initialized on the third PICLK after LOCKDET goes active. The PCLK-to-PICLK delay (tD) can have any value before the FIFO is initialized. The tD is fixed at the third PICLK after LOCKDET goes active. Once the FIFO is initial- ized, PCLK and PICLK cannot drift more than 5.2 ns; tCH cannot be more than 5.2 ns. Figure 8. PCLK-to-PICLK Timing PCLK PICLK LOCKDET ACTIVE 3RD IS INITALIZED AT THE THIRD RISING EDGE OF PICLK AFTER LOCKDET GOES ACTIVE. PCLK-TO-PICLK DELAY IS FIXED AND FIFO 2ND 1ST tCH tCH tD tD 1-1123(F) |
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