2

2

Agere Systems Inc.

1345-Type Receiver with

Data Sheet

Clock Recovery and Data Retiming

January 2000

The receiver converts optical signals in the range of

1.1

µm to 1.6 µm into retimed clock and data signals.

The clock and data outputs are raised-ECL (PECL)

logic levels. A CMOS-level flag output indicates when

there is a loss of optical signal.

The receiver requires a 5 V power supply for the ampli-

fier, logic, and PLL CRC circuits. The operating case

temperature range is –40 °C to +85 °C.

Pin 10

Pin 10 on the 1345-Type receiver is not an internally

connected (NIC) pin. This definition allows the 1345 to

be used in most customer 20-pin receiver module

applications. Customer’s printed-wiring boards that are

designed with ground, +5 V, –5 V, or no connection to

this pin are all acceptable options. For those applica-

tions that require monitoring the photocurrent of the

PIN photodetector for power monitoring purposes,

there are versions of the 1345 that require +5 V or –5 V

applied to Pin 10. Check Tables 3 and 4 for ordering

information.

Flag Output

When the optical input falls below the link status flag

switching threshold, the link status flag is deactivated

and its output logic level changes from a CMOS logic

HIGH to a CMOS logic LOW.

Squelched Data and Clock Outputs

In some versions of the 1345 receiver (see Table 4),

when the link status flag is deactivated, the data and

clock outputs are squelched (stop outputting a signal).

When this occurs, the DATA, DATA, CLOCK, and

CLOCK outputs switch to a constant dc output voltage

level of 1.3 V.

Nonsquelched Data and Clock Outputs

Agere Systems also manufactures nonsquelching ver-

sions of the 1345 receiver for those applications that

require the data and clock outputs to continue to func-

tion after the link status flag is deactivated. In those

versions of the receiver, when the link status flag is

deactivated, a signal will continue to appear at the

DATA, DATA, CLOCK, and CLOCK outputs. See Table 4

for nonsquelching codes.

1-724(C)

Figure 1. Block Diagram

FILTER

Si

PREAMPLIFIER

InGaAs

PIN

SILICON BIPOLAR

LIMITING AMPLIFIER

5 V

DATA

DATA

SILICON BIPOLAR

DECISION CIRCUIT

FLAG

PLL TIMING

RECOVERY UNIT

CLOCK

CLOCK

FLAG