R4400PC datasheet(5/11 Pages) AEROFLEX

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SCD4430 Rev A 11/18/96

7.0 Signal Descriptions

System Interface Signals

SysAD(63:0)

I/O

System address/data bus

: A 64 bit address and data

bus for communication between the processor and an

external agent

SysADC(7:0)

I/O

System address/data check bus:

An 8 bit bus contain-

ing check bits for the SysAD bus

SysCmd(8:0)

I/O

System command/identifier bus parity:

A 9 bit bus for

command and data identifier transmission between the

processor and an external agent

SysCmdP

I/O

System command /data identifier bus parity

: A single,

even parity bit for thr SysCmd bus

Validin*

Valid Input:

An external agent asserts ValidIn* when it

is driving a valid address or data on the SysAD bus and

a valid command or data identifier on the SysCmd bus

ValidOut*

Valid Output

: The processor asserts ValidOut* when it

is driving a valid address or data on the SysAD bus and

a valid command or data identifier on the SYSCMD bus

ExtRqst*

External Request:

An external agent asserts ExtRqst* to

request the use of the system interface. The processor

grants the request by asserting Release*

Release*

Release Interface:

In response to the assertion of

ExtRqst*, the processor asserts Release* to signal the

requesting device that the system interface is available

RdRdy*

Read ready:

The external agent asserts RdRdy*to indi-

cate that it can accept processor read, invalidate, or

update requests in both overlap and non-overlap mode

or can accept a read followed by a potential invalidate

or update request in the overlap mode

WrRdy*

Write ready:

An external agent asserts WrRdy* when it

can accept a processor write request

IvdAck*

Invalidate acknowledge:

An external agent asserts

IvdAck* to signal successful completion of a processor

invalidate or update request (MC only)

IvdErr*

Invalidate error

: An external agent asserts InvErr* to

signal unsuccessful completion of a processor invali-

date or update request(MC only)

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