MT70003

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

4

Arinc 429 Word Structure

An Arinc 429 word is 32 bits long. The first part of the word to be transmitted is the lable (tag) of which bit

1 is the most significant and bit 8 the least significant. Bits 9 and 10 are reserved for the source/destination

identifier in some formats otherwise they are used as data pad bits. When circuit input IDENTIFIER is

wired HI bits 9 & 10 are treated as extra tag bits and contribute to address recognition but when IDENTIFIER

is wired LO bits 9 & 10 are excluded from address recognition.

Bits 11 to 29 are the data field of which bit 11 is the least significant, Bits 30 and 31 are reserved for the

sign/status matrix and bit 32 is the parity bit.

µ

For high speed operation the bit rate must be 100 Kilobits per second + 1% and circuit input FAST/SLOW

SELECT must be wired LO. For low speed operation the bit rate must be in the range 12.0 to 14.5 Kilobits

per second and the selected rate should be maintained within 1%. FAST/SLOW SELECT must then be wired

HI.

Internal Timing

This is determined by a 1 Mhz clock applied to

be maintained within + 10%.

Word Synchronisation

The digital word is synchronised by reference to a gap of 4 bit times (minimum) between words. The

beginning of the first transmitted bit following the gap signifies the beginning of the next word.

Spike Rejection (Timing asumes clock period = 1

µs)

The circuit incorporates pulse rejection filters on both inputs. This will reject pulses less than 2

µs duration

and accept pulses greater than 3

µs duration.

Internal Address Recognition

If MODE SELECT is wired LO internal address recognition is performed during the sequencer period.

during the sequencer period. If IDENTIFIER is LO the states input on T1 to T8 are internally compared with

bits 1 to 8 of the tag latch and only if they are equivalent within 4

µs of TAG VALID being set is the address

recognised. Although the states on T9 and T10 are ignored, these inputs should be held at good logic levels

otherwise the circuit supply current could increase.

If IDENTIFIER is HI then T9 and T10 are also compared against 9 & 10 of the tag latch.

With MODE SELECT held LO the conditions on input pins ADDRESS RECOGNISED and TAG ENABLE

are ignored. Since these pins have internal pull-up transistors they need not be connected if not required.

External Address Recognition (Timing assumes clock period = 1

µs )

If MODE SELECT is wired HI the internal address comparator is inhibited. T1 to T10 respond as tri-state

output ports enabled whenever NOTTAG ENABLE is LO. Then the contents of the tag latch are presented to

the tag output bus.

The normal sequence of operations in this mode is for TAG VALID to be set at the end of a good word. The

user takes this as a singla to interrogate the tag latch by enabling the tristates. Within 4

µs of TAG VALID

going HI a decision is taken whether or not to load the word latch via ADDRESS RECOGNISED.