ACT7005 datasheet(14/29 Pages) AEROFLEX

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SCD7005 REV B 8/2/01

Plainview NY (516) 694-6700

Name

Use

VECTOR

Indicates that a transmit VECTOR mode command has been received.

VECTOR DATA is transmitted from VW/CMD WD #2/AMD Register.

DBCREQ

Indicates acceptance of DYNAMIC BUS CONTROL COMMAND REQUEST

Note: RTU will not accept valid DBC mode command unless DBCACC bit

is set low in the OPERATION Register.

RETRY

Indicates that an error has occurred in the data transfer and that a retry will be

performed if the retry option is selected. If all retries that were selected fail,

INVALID TRANSFER INTERRUPT would be asserted on the final failure.

SELF TEST

Indicates that the INITIATE SELF TEST mode command is being serviced.

PASS

Active low pulse output signal which indicates that a sub-system initiated

self-test (on-or off-line) operation has been sucessfully completed. This

interrupt will be issued approximately 90µs after the self-test operation has

been triggered.

Table 6 – Discrete Interrupts Summary (continued)

Bit

Name

Function

0-4

SA BITS

SUBADDRESS BITS

Define SUBADDRESS MESSAGE BLOCK in INTERNAL RAM.

BIT

SUBADDRESS BIT

SA0 (LSB)

SAl

SA2

SA3

SA4 (MSB)

These bits correspond directly to 1553B definition in the command word.

Although SUBADDRESSES 00000B and 11111B are illegal in 1553B, message

blocks specified by them are both READABLE and WRITABLE by the

SUBSYSTEM. They are not accessible from the 1553B BUS.

5T/R BIT

TRANSMIT/RECEIVE BIT points INPUT/OUTPUT OPERATIONS to either the

TRANSMIT SECTION or RECEIVE SECTION of the INTERNAL RAM.

I/O

INPUT/OUTPUT BIT DEFINES DIRECTION OF DATA TRANSFER

1. SET HIGH: INPUT OPERATION

An EXECUTE operation will transfer the Data currently loaded in the input

FIFO buffer to the specified message block (SUBADDRESS) in the internal

RAM.

Between 1 and 32 data words must be loaded in the input FIFO buffer when

using an EXECUTE command with this bit set.

2. SET LOW: OUTPUT OPERATION

EXECUTE operation will transfer a complete block of data (32 words) to the

output FIFO buffer from the specified subaddress of internal RAM.

Table 7 – Operational Register

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