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LTP5902-IPR датащи(PDF) 19 Page - Linear Technology |
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LTP5902-IPR датащи(HTML) 19 Page - Linear Technology |
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19 / 29 page ![]() A d v a nce d I n fo rm a t i o n Eterna Datasheet Linear Technology / Dust Networks 19 VOH (high-level output voltage) High Drive IOH(max) = −6.3 mA VSUPPLY - 0.3 † VSUPPLY + 0.3 † V Input leakage current 50 nA † Min and Min and Max IO input levels must respect the Minimum and Maximum voltages for VSUPPLY. 8.6 Temperature Sensor Characteristics The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Table 11 Temperature Sensor Characteristics Parameter Conditions Min Typ Max Units Offset Temperature offset error at 25 ºC ±0.25 °C Slope error Slope error from -40 to +85 ºC ±0.033 °C/°C 8.8 System Characteristics The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Table 13 System Characteristics Parameter Conditions Min Typ Max Units Doze to Active state delay 5 µs Doze to Radio TX or RX 1.2 ms QCCA charge to sample RF channel Start from Doze state 4 µC Radio baud rate 250 kbps RESETn pulse width 125 µs 8.9 UART AC Characteristics The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Table 14 UART Timing Values Parameter Conditions Min Typ Max Unit tRX_BAUD Deviation from baud rate –2 +2 % tTX_BAUD Deviation from baud rate –1 +1 % tRX_RTS_R to RX_CTS Assertion of UART_RX_RTSn to assertion of UART_RX_CTSn, or negation of UART_RX_RTSn to negation of UART_RX_CTSn 0 22 ms tCTS_R to RX Assertion of UART_RX_CTSn to start of byte 0 20 ms tEOP to RX_RTS End of packet (end of the last stop bit) to negation of UART_RX_RTSn 0 22 ms tTX_RTS_T to TX_CTS Assertion of UART_TX_RTSn to assertion of UART_TX_CTSn, or negation of UART_TX_RTSn to negation of UART_TX_CTSn 0 22 ms tTX_CTS_T to TX Assertion of UART_TX_CTSn to start of byte 0 2 bit period tEOP to TX_RTS End of packet (end of the last stop bit) to negation of UART_TX_RTSn 0 1 bit period tRX_INTERBYTE Receive Inter-byte delay 100 ms tTX to TX_CTS Start of byte to negation of UART_TX_CTSn 0 ms tINTERPACKET Transmit and Receive Inter-packet delay (Mode 4 only) 100 ms |
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