A d v a nce d I n fo rm a t i o n

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Linear Technology / Dust Networks

Eterna Datasheet

and enters the serial flash emulation mode, if both signals are asserted. If the FLASH_P_ENn pin is not asserted but RESETn

asserted, Eterna goes through a boot sequence, and then enters the Active state.

4.1.1

Fuse Table

Eterna’s Fuse Table is a 2 KB page in flash that contains two data structures, one for hardware configuration immediately

following Power on Reset or the assertion of RESETn and one for configuration of design specific parameters. Hardware

support for configuration includes configuration of I/O, preventing I/O leakage from negatively affecting current

consumption during power on, which can be a significant issue for current limited supplies. Examples of design-specific

parameters include setting of UART modes, clock sources and trim values. Fuse Tables are created via the Fuse Table

application software described in 040-0109 Design Specific Configuration Guide. Fuse Tables are loaded into flash using the

same software and in-circuit programmer used to load Eterna’s networking software image – see the 040-0110 Eterna Serial

Programmer Guide for details.

4.2

Serial Flash Emulation

When both RESETn and FLASH_P_ENn are asserted, Eterna disables normal operation and enters a mode to emulate the

operation of a serial flash. In this mode, its flash can be programmed with software updates. For details, see Section 2.10.

4.3

Operation

Once Eterna has completed startup, Eterna transitions to the Operational group of states (active / CPU active, active / CPU

inactive, and Doze). There, Eterna cycles between the various states, automatically selecting the lowest power state possible

while fulfilling the demands of network operation.

4.3.1

Active State

In Active state, the Eterna’s relaxation oscillator is running and peripherals are enabled as needed. The ARM Cortex-M3

cycles as needed between CPU-active and CPU-inactive (referred to in the ARM Cortex-M3 literature as “Sleep Now” or

“Sleep on Exit” modes). Eterna’s extensive use of DMA and intelligent peripherals that can independently move Eterna

between the Active and Doze states minimizes the time the CPU is active, significantly reducing Eterna’s energy

consumption.

4.3.2

Doze State

The Doze state consumes orders of magnitude less current than the Active state (see Table 6) and is entered when all of the

peripherals, save the low power portion of the timer module, and the CPU are inactive. In the Doze state Eterna’s full state is

retained and Eterna is configured to detect, wake, and rapidly respond to activity on I/Os (such as UART signals and the

TIMEn pin). The Doze state also uses the 32.768-kHz oscillator and 32 kHz based timers are active.