LTC4151 datasheet(14/32 Pages) LINER

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LTC2945

2945f

APPLICATIONS INFORMATION

Storing Minimum and Maximum Values

The LTC2945 compares each measurement including the

calculated power with the stored values in the respective

MIN and MAX registers for each parameter (Table 2). If

the new conversion is beyond the stored minimum or

maximum values, the MIN or MAX registers are updated

with the new values. The MIN and MAX of the registers are

refreshed at the end of their respective ADC conversions

in both continuous scan mode and snapshot mode. They

are also refreshed if the ADC registers are written via the

I2C bus with values beyond the stored values. To initiate

a new peak hold cycle, write all 1’s to the MIN registers

and all 0’s to the MAX registers via the I2C bus. These

registers will be updated when the next respective ADC

conversion is done.

The LTC2945 also includes MIN and MAX THRESHOLD

registers (Table 2) for the measured parameters including

the calculated power. At power-up, the maximum thresh-

olds are set to all 1’s and minimum thresholds are set to

all 0’s, effectively disabling them. The thresholds can be

reprogrammed to any desired value via the I2C bus.

Fault Alert and Resetting Faults

As soon as a measured quantity falls below the minimum

threshold or exceeds the maximum threshold, the LTC2945

sets the corresponding flag in the STATUS register and

latches it into the FAULT register (see Figure 4). The ALERT

pin is pulled low if the appropriate bit in the ALERT register

is set. More details on the alert behavior can be found in

the Alert Response Protocol section.

An active fault indication can be reset by writing zeros

to the corresponding FAULT register bits or by reading

the FAULT CoR register (Table 2), which clears all FAULT

VDD and INTVCC fall below their respective I2C logic reset

threshold. Note that faults that are still present, as indi-

cated in the STATUS registers, will immediately reappear.

I2C Interface

The LTC2945 includes an I2C/SMBus-compatible inter-

face to provide access to the onboard registers. Figure 5

shows a general data transfer format using the I2C bus.

The LTC2945 is a read-write slave device and supports

the SMBus Read Byte, Write Byte, Read Word and Write

Word protocols. The LTC2945 also supports extended

Read and Write commands that allow reading or writing

more than two bytes of data. When using the Read/Write

Word or extended Read and Write commands, the bus

master issues an initial register address and the internal

after each byte of data is read or written. After the register

address reaches 31h, it will roll over to 00h and continue

incrementing. A Stop condition resets the register address

pointer to 00h. The data formats for the above commands

are shown in Figures 6 to 11.

I2C Device Addressing

Nine distinct I2C bus addresses are configurable using the

three-state pins ADR0 and ADR1, as shown in Table 1.

ADR0 and ADR1 should be tied to INTVCC, to GND, or left

floating (NC) to configure the lower four address bits.

During low power shutdown, the address select state

is latched into memory powered from standby supply.

Address bits a6, a5 and a4 are permanently set to (110)

and the least significant bit is the R/W bit. In addition, all

LTC2945 devices will respond to a common Mass Write

address (1100 110)b; this allows the bus master to write

to several LTC2945s simultaneously, regardless of their

individual address settings. The LTC2945 will also respond

to the standard ARA address (0001100)b if the Alert pin

is asserted; see the Alert Response Protocol section for

more details. The LTC2945 will not respond to the ARA

address if no alerts are pending.

Start and Stop Conditions

When the I2C bus is idle, both SCL and SDA are in the high

state. A bus master signals the beginning of a transmission

with a Start condition by transitioning SDA from high to

low while SCL stays high. When the master has finished

communicating with the slave, it issues a Stop condition

by transitioning SDA from low to high while SCL stays

high. The bus is then free for another transmission.

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