TMP01

REV. C

–4–

WAFER TEST LIMITS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUTS SET HIGH, SET LOW

Input Bias Current

100

nA

OUTPUT VPTAT

Temperature Accuracy

°C, No Load

1.5

°C

OUTPUT VREF

Nominal Value

VREF

2.490

2.510

V

Line Regulation

4.5 V

≤ V+ ≤ 13.2 V

±0.05

%/V

Load Regulation

10

µA ≤ I

VREF

≤ 500 µA

±0.25

%/mA

OPEN-COLLECTOR OUTPUTS OVER, UNDER

Output Low Voltage

0.4

mV

Output Low Voltage

1.0

V

Output Leakage Current

100

µA

POWER SUPPLY

Supply Range

V+

4.5

13.2

V

Supply Current

Unloaded

600

µA

NOTES

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

DICE CHARACTERISTICS

Die Size 0.078

× 0.071 inch, 5,538 sq. mils

(1.98

× 1.80 mm, 3.57 sq. mm)

Transistor Count: 105

For additional DICE ordering information, refer to databook.

8

7

6

5

1

2

3

4

4

1. VREF

2. SETHIGH

3. SETLOW

4. GND (TWO PLACES)

(CONNECTED TO SUBSTRATE)

5. VPTAT

6. UNDER

7. OVER

8. V+