SSM2120/SSM2122

REV. C

–4–

2V

FULL

WAVE

RECTIFIER

V+

THRESH

LOG AV

V–

Q1

Q2

1k

Ω

39k

Ω

200

Ω

INPUT

V–

Figure 3. Level Detector

Note: It is natural to assume that with the addition of the

averaging capacitor, the LOG AV output would become the

capacitor forces an ac ground at the emitter of the output

transistor, the capacitor charging currents are proportional to

the antilog of the voltage at the base of the output transistor.

Since the base voltage of the output transistor is the log of the

capacitor becomes a linear integrator with a charging current

directly proportional to the absolute value of the input current.

This effectively inverts the order of the averaging and logging

functions. The signal at the output therefore is the log of the

resistor should be followed by a low leakage blocking capacitor

±1.5 mA peak signal. For ±15 V

operation this corresponds to a value of 10 k

Ω.

A 1.5 M

Ω value of R

a 10

µA reference current in the logging transistor (Q

will bias the transistor in the middle of the detector’s dynamic

current range in dB to optimize dynamic range and accuracy.

The LOG AV outputs are buffered and amplified by unipolar

drive op amps. The 39 k

Ω, 1 kΩ resistor network at the

THRESH pin provides a gain of 40.

appropriate VCA control port establishes the control sensitivity.

Use 200

Ω for the attenuator resistor to ground and choose

or capacitive loads are present, it is best to connect the series

DYNAMIC LEVEL DETECTOR CHARACTERISTICS

Figures 4 and 5 show the dynamic performance of the level

detector to a change in signal level. The input to the detector (not

shown) is a series of 500 ms tone bursts at 1 kHz in successive

10 dBV steps. The tone bursts start at a level of –60 dBV (with

step. Tone bursts range from –60 dBV to +10 dBV. Figure 4

shows the logarithmic level detector output. The output of the

detector is 3 mV/dB at LOG AV and the amplifier gain is 40

to increase by 1.2 V for each 10 dBV increase in input level.

TRIMMING THE VCAs

The control feedthrough (CFT) pins are optional control feed-

through null points. CFT nulling is usually required in applications

such as noise gating and downward expansion. If trimming is

not used, leave the CFT pins open.

Trim Procedure

1. Apply a 100 Hz sine wave to the control point attenuator.

The signal peaks should correspond to the control voltages

which induce the VCAs maximum intended gain and at least

30 dB of attenuation.

2. Adjust the 50 k

Ω potentiometer for the minimum

feedthrough.

(Trimmed control feedthrough is typically well under 1 mV rms

when the maximum gain is unity using 36 k

Ω input and output

resistors.)

Applications such as compressor/limiters typically do not require

control feedthrough trimming because the VCA operates at

unity-gain unless the signal is large enough to initiate gain

reduction. In this case the signal masks control feedthrough.

This trim is ineffective for voltage-controlled filter applications.

LEVEL DETECTION CIRCUITS

The SSM2120 contains two independent level detection

circuits. Each circuit contains a wide dynamic range full-wave

rectifier, logging circuit and a unipolar drive amplifier. These

circuits will accurately detect the input signal level over a

100 dB range from 30 nA to 3 mA peak-to-peak.

LEVEL DETECTOR THEORY OF OPERATION

Referring to the level detector block diagram of Figure 3, the

ments the full-wave rectification of the input current. This

AV output is then:

kT

q

ln









With the use of the LOG AV capacitor the output is then the log

(The unfiltered LOG AV output has broad flat plateaus with

sharp negative spikes at the zero crossing. This reduces the

“work” that the averaging capacitor must do, particularly at low

frequencies.)