REV. 0

EVAL-AD1852EB

–2–

FUNCTIONAL DESCRIPTION

The AD1852 evaluation board presents a reference design that

can be used as a suggested layout and circuit implementation,

which will deliver optimal performance from the audio DAC. As

far as is possible on an evaluation board, current assembly methods

and components are used. Most components are surface mount

devices and a four-layer printed circuit board is used with full

internal power and ground planes for best noise performance.

For guidance, a schematic, bill of materials, PLD source code,

and PCB plots are included in this document.

POWER SUPPLIES

The PC board is divided into analog and digital sections, each

with separate power supplies, to facilitate testing. The digital

power supply input is via binding post terminals J8 and J9. The

recommended digital supply is 12 V dc at 110 mA

± 25 mA. An

on-board voltage regulator (U6) provides 5 V dc,

± 5% to the

digital circuitry. The analog power supply inputs are binding

posts, J10, J11, and J12. Recommended analog supply is 12 V

dc at 50 mA

± 10 mA and –12 V dc at –20 ± 5 mA. An on-

board, low noise voltage regulator, (U7) provides 5 V dc,

±5%

to the analog power pins of the AD1852 DAC.

DIGITAL AUDIO SIGNAL INPUTS

RCA phone jack, (J1) and optical TOSLink input (U1) may be

used for standard SPDIF or AES/EBU input signals. J1 is termi-

nated with a 75

Ω resistor. Switch S1 selects between J1 and U1

inputs and feeds the selected signal to the digital interface receiver

(U2). Switch SPDIF/EXT (S3) controls CPLD (U4) and U11,

which is used to switch signals between the SPDIF input (J1)

and the direct input, via the 10-pin header J2, EXT DATA

INTERFACE.

The EXT DATA INTERFACE input permits buffered (U4,

M4–64/32 and U11, HC00) access to the BCLK, L/

RCLK,

SDATA and MCLK inputs to the AD1852 DAC. This permits

testing with left-justified, I

Note that with right-justified input data, the AD1852 control

register must be programmed for the correct number of data

bits, i.e., 16, 20 or 24 bits. When using the direct input header,

it is necessary to provide all four signals, MCLK, BCLK, L/

RCLK

and SDATA. A termination network (RC1), consisting of a series

connected 100

Ω resistor and a 47 pF capacitor, is shunted

across each signal line to reduce line reflections. A 10 k

Ω pull-

up network (RT1) ensures the inputs are not floating in the

absence of an external data source.

EXTERNAL SPI CONTROL PORT

An external control port, SPI CONTROL PORT (J3), is pro-

vided, via a 10-pin header, so that the internal volume controls

and control registers can be programmed from an external host

or microcontroller. This port accepts serial data to indepen-

dently set the left/right volume or the operating mode of the

AD1852 by programming the contents of three internal 16-bit

registers. When setting the volume, a 16-bit control word has

14 bits allocated to the left or right volume control, giving a

total range of 84 dB. Details of the signal format and timing are

discussed in the AD1852 data sheet.

An additional connector, PC PORT (J5), has been provided to

permit connection to the parallel port of a computer. A termi-

nation network (RC2) consisting of a series-connected 100

Ω

resistor and a 47 pF capacitor, is shunted across each signal line

to reduce line reflections. Additionally, a Schmitt trigger (U5)

reduces the effects of noise and line reflections. A 10 k

Ω pull-up

network (RT2) ensures the inputs are not floating in the absence

of an external data source.

PC LabView software (LVAD1852EB.zip) can be downloaded

from the Analog Devices, Inc., Digital Audio website, (http://

www.analog.com/techsupt/eb/lin_eb/ad1852/ad1852.html) to

program the internal control registers and set the left and right

volume levels. An interface cable connects between the PC

parallel printer port (LPTn) 25-pin Dsub connector and the

9-pin Dsub (J5) connector on the evaluation board. A suitable

cable is Belkin Modem cable, part number 589604, F2L088-06

The pin-out for this cable in shown, in the table below, for users

who wish to make their own cable.

Table I.

PC

EVAL Board

Function

(DB-25 Male)

(DB-9 Female)

Data 6

8

1

Data 1

3

2

Data 0

2

3

GND

20

4

Data 5

7

5

Data 4

6

6

Data 2

4

7

Data 3

5

8

GND

22

9

Chassis Shield GND

Case

Case

NOTE: When setting the internal control registers via the SPI

port, it is essential to pull the corresponding external pins low as

they are wire-OR’d with the SPI control registers. This applies

to the interpolation mode pins, via JP1 (192/

48 P7, 96/48 P10),

the power down/reset pin, (

RESET), the mute pin, (MUTE), the

interface mode pins (IDPM1, IDPM0) and the de-emphasis

control pin, (DEEMPH). Also note that when the right-justified

interface mode is selected, either via the external pins or via the

SPI port, the default data word width is 24 bits. It is necessary

to select 16 or 20 bits via the SPI control register if these word

lengths are required.

AUDIO SIGNAL OUTPUTS

RCA jacks J6 and J7 provide LEFT and RIGHT audio output

signals. The output is filtered with a low-pass anti-image filter

using an OP275 audio op amp (U9) which also converts the dif-

ferential outputs of the AD1852 to single ended signals. The

filter –3 dB cut-off frequency is 100 kHz and has an approxi-

mate Third Order Bessel (linear phase) response. The output

source impedance is approximately 600

Ω. The full-scale output

signal is 2 V rms (5.6 V p-p).