DAC8222

–9–

REV. C

Table I. Mode Selection

Digital Inputs

Register Status

DAC A

DAC B

DAC

A/B

WR

LDAC

Input Register

DAC Register

Input Register

DAC Register

L

L

L

WRITE

WRITE

LATCHED

WRITE

H

L

L

LATCHED

WRITE

WRITE

WRITE

L

L

H

WRITE

LATCHED

LATCHED

LATCHED

H

L

H

LATCHED

LATCHED

WRITE

LATCHED

X

H

L

LATCHED

WRITE

LATCHED

WRITE

X

H

H

LATCHED

LATCHED

LATCHED

LATCHED

L = Low, H = High, X = Don’t Care

WRITE TIMING CYCLES

Two timing diagrams are shown and are at the user’s discretion

which to use.

The TWO-CYCLE UPDATE, as the name implies, allows both

DAC registers to be loaded and the outputs updated in two

cycles. Data is first loaded into one DAC’s input register on the

first write cycle, and then new data loaded into the other DAC’s

input register while simultaneously updating both DAC outputs

on the second cycle.

The THREE-CYCLE UPDATE allows

DAC A and DAC B

registers to be loaded and analog output to be updated at a later

time. The first two cycles load both DACs as above, and the

third cycle updates the outputs.

The

LDAC and DAC A/DAC B control pins can be tied to-

gether and controlled with a single strobe. When using the DAC

in this configuration, DAC B must be loaded first.

INTERFACE CONTROL LOGIC

DAC A/DAC B (Pin 18)–DAC Selection. Active low for

DAC A and active high for DAC B.

WR (Pin 20)–WRITE. Active Low. Used to write data into

either DAC A or DAC B input registers, or active high latches

data into the input registers.

LDAC (Pin 19)–LOAD DAC. Active Low. Used to simulta-

neously transfer data from

DAC A and DAC B input registers

to both DAC outputs. The DAC becomes transparent (activity

on the digital inputs appear at the analog output) when both

WR and LDAC are low. Data is latched into the output regis-

ters on the rising edge of

LDAC.

Three-Cycle Update

Figure 23. Write Cycle Timing Diagram

Two-Cycle Update