ADV7152

–17–

REV. B

Table IV. Interface Truth Table (8-Bit Databus Mode)*

Databus

R/W

C1

C0

(D9–D0)

Operation

Result

0

1

1

DB7–DB0

Write to Mode Register

DB7–DB0 ¡ MR17–MR10

0

0

0

DB7–DB0

Write to Address Register

DB7–DB0 ¡ A7–A0

0

1

0

DB7–DB0

Write to Control Registers

DB7–DB0 ¡ Control Registers

(Particular Control Register Determined by Address Register (A7–A0))

0

0

1

DB9–DB2

Write to RED Register

DB9–DB2 ¡ R9–R2

0

0

1

DB1–DB0

Write to RED Register

DB1–DB0 ¡ R1–R0

0

0

1

DB9–DB2

Write to GREEN Register

DB9–DB2 ¡ G9–G2

0

0

1

DB1–DB0

Write to GREEN Register

DB1–DB0 ¡ G1–G0

0

0

1

DB9–DB2

Write to BLUE Register

DB9–DB2 ¡ B9–B2

0

0

1

DB1–DB0

Write to BLUE Register

DB1–DB0 ¡ B1–B0

Write RGB Data to RAM Location Pointed to by Address Register (A7-A0)

Address Register = Address Register + 1

1

1

1

DB7–DB0

Read Mode Register

MR17–MR10 ¡ DB7–DB0

1

0

0

DB7–DB0

Read Address Register

A7–A0 ¡ DB7–DB0

1

1

0

DB7–DB0

Read Control Registers

Register Data ¡ DB7–DB0

(Particular Control Register Determined by Address Register)

1

0

1

DB9–DB2

Read RED RAM Location

R9–R2 ¡ DB9–DB2

1

0

1

DB1–DB0

Read RED RAM Location

R1–R0 ¡ DB1–DB0

1

0

1

DB9–DB2

Read GREEN RAM Location

G9–G2 ¡ DB9–DB2

1

0

1

DB1–DB0

Read GREEN RAM Location

G1–G0 ¡ DB1–DB0

1

0

1

DB9–DB2

Read BLUE RAM Location

B9–B2 ¡ DB9–DB2

1

0

1

DB1–DB0

Read BLUE RAM Location

B1–B0 ¡ DB1–DB0

(RAM Location Pointed to by Address Register (A7–A0))

Address Register = Address Register + 1

*Writing or reading 10-bit data (DB9–DB0) over an 8-bit databus (D7–D0) requires two write or two read cycles.

:DB9–DB2 is mapped to D7–D0 on the first cycle.

:DB1–DB0 is mapped to D1–D0 on the second cycle.

DB = Data Bit.

Power-On Reset

On power-up of the ADV7152 executes a power-on reset opera-

tion. This initializes the pixel port such that the pixel sequence

AB starts at A. The Mode Register (MR17–MR10), Command

Register 2 (CR27–CR20) and Command Register 3 (CR37–

CR30) have all bits set to a Logic “1.” Command Register 1

(CR17–CR10) has all bits set to a Logic “0.”

The output clocking signals are also set during this reset period.

PRGCKOUT = CLOCK/32

LOADOUT = CLOCK/2

5 V. This reset is active for 1

µs. The ADV7152 should not be

accessed during this reset period. The pixel clock should be

applied at power-up.