ADV7150LS170 datasheet(27/36 Pages) AD

27 / 36 page

ADV7150

–27–

REV. A

Digital Signal Interconnect

The digital inputs to the ADV7150 should be isolated as much

as possible from the analog outputs and other analog circuitry.

Also, these input signals should not overlay the analog power

plane.

Due to the high clock rates involved, long clock lines to the

ADV7150 should be avoided to reduce noise pickup.

Any active termination resistors for the digital inputs should be

connected to the regular PCB power plane (VCC), and not the

analog power plane.

Analog Signal Interconnect

The ADV7150 should be located as close as possible to the out-

put connectors to minimize noise pick-up and reflections due to

impedance mismatch.

The video output signals should overlay the ground plane, and

not the analog power plane, to maximize the high frequency

power supply rejection.

Digital Inputs, especially Pixel Data Inputs and clocking signals

(CLOCK, LOADOUT, LOADIN, etc.) should never overlay

any of the analog signal circuitry and should be kept as far away

as possible.

For best performance, the analog outputs (IOR, IOG, IOB)

should each have a 75

Ω load resistor connected to GND.

These resistors should be placed as close as possible to the

ADV7150 so as to minimize reflections. Normally, the differen-

tial analog outputs (IOR, IOG, IOB) are connected directly to

GND. In some applications, improvements in performance are

achieved by terminating these differential outputs with a resis-

tive load similar in value to the video load. For a doubly termi-

nated 75

Ω load, this means that IOR, IOG, IOB are each

terminated with 37.5

Ω resistors.

APPENDIX 2

TYPICAL FRAME BUFFER INTERFACE

CLOCK

ADV7150

CLOCK

LOADOUT

PRGCKOUT

LOADIN

SCKOUT

SCKIN

BLANK

LATCH

ENABLE

SYNC

ECL

TTL

DIVIDE BY N

(

÷ N)

VRAM

(BANK A)

VRAM

(BANK B)

FRAME

BUFFER/

VIDEO

MEMORY

MULTIPLEXER

PALETTE/RAM

& DAC

BLANK

SYNC

CLOCK

GRAPHICS

PROCESSOR/

CONTROLLER

VRAM

(BANK C)

VRAM

(BANK D)

33MHz

DIVIDE BY M

(

÷ M)

CLOCK

GENERATOR

ADV7150LS170 датащи(PDF) 27 Page - Analog Devices

ADV7150LS170 датащи(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL