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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADSP2185 датащи(PDF) 17 Page - Analog Devices |
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ADSP2185 датащи(HTML) 17 Page - Analog Devices |
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17 / 32 page  ADSP-2185 REV. 0 –17– TIMING PARAMETERS Parameter Min Max Unit Clock Signals and Reset Timing Requirements: tCKI CLKIN Period 60 150 ns tCKIL CLKIN Width Low 20 ns tCKIH CLKIN Width High 20 ns Switching Characteristics: tCKL CLKOUT Width Low 0.5 tCK – 7 ns tCKH CLKOUT Width High 0.5 tCK – 7 ns tCKOH CLKIN High to CLKOUT High 0 20 ns Control Signals Timing Requirements: tRSP RESET Width Low 1 5 tCK ns tMS Mode Setup Before RESET High 2 ns tMH Mode Setup After RESET High 5 ns NOTE 1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKCH tCKI tCKIH tCKIL tCKH tCKL tMH tMS CLKIN CLKOUT PF(2:0) * RESET *PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 14. Clock Signals |
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