CPC7592BBTR datasheet(15/19 Pages) IXYS

15 / 19 page

INTEGRATED CIRCUITS DIVISION

CPC7592

R04

www.ixysic.com

Forcing TSD to a logic high disables the thermal

shutdown circuit and is therefore not recommended as

this could lead to device damage or destruction in the

presence of excessive tip or ring potentials.

Break-Before-Make Ringing to Talk Transition Logic Sequence for all Versions

2.4 Data Latch

The CPC7592 has an integrated transparent data

latch. The latch enable operation is controlled by TTL

logic input levels at the LATCH pin. Data input to the

latch is via the input pins INRINGING and INTEST while

the output of the data latch are internal nodes used for

state control. When the LATCH enable control pin is at

a logic 0 the data latch is transparent and the input

control signals flow directly through the data latch to

the state control circuitry. A change in input will be

reflected by a change in the switch state.

Whenever the LATCH enable control pin is at logic 1,

the data latch is active and data is locked. Subsequent

changes to the input controls INRINGING and INTEST

will not result in a change to the control logic or affect

the existing switch state.

The switches will remain in the state they were in

when the LATCH changes from logic 0 to logic 1 and

will not respond to changes in input as long as the

LATCH is at logic 1. However, neither the TSD input

nor the TSD output control functions are affected by

the latch function. Since internal thermal shutdown

control and external “All-off” control is not affected by

the state of the LATCH enable input, TSD will override

state control.

2.5 TSD Pin Description

The TSD pin is a bi-directional I/O structure with an

internal pull-up current source with a nominal value of

A biased from V

DD. As an output, this pin

indicates the status of the thermal shutdown circuitry.

Typically, during normal operation, this pin will be

pulled up to VDD but under fault conditions that create

excess thermal loading the CPC7592 will enter

thermal shutdown and a logic low will be output.

As an input, the TSD pin is utilized to place the

CPC7592 into the “All-Off” state by simply pulling the

input low. For applications using low-voltage logic

devices (lower than VDD), IXYS IC Division

recommends the use of an open-collector or an

open-drain type output to control TSD. This avoids

sinking the TSD pull up bias current to ground during

normal operation when the all-off state is not required.

In general, IXYS IC Division recommends all

applications use an open-collector or open-drain type

device to drive this pin.

Setting TSD to a logic 1 or tying this pin to VCC allows

switch control using the logic inputs. This setting,

however, also disables the thermal shutdown circuit

and is therefore not recommended. As a result the

TSD pin has two recommended operating states when

it is used as an input control. A logic 0, which forces

State

INRINGING

INTEST

LATCH

TSD

Timing

Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing

Off

All-Off

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero current to

turn off.

Off

Break-

Before-

Make

SW4 has opened

Off

Talk

Close Break Switches

Off

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