ADP3605

–5–

REV. A

THEORY OF OPERATION

The ADP3605 uses a switched capacitor principle to generate a

negative voltage from a positive input voltage. An onboard

oscillator generates a two phase clock to control a switching

network that transfers charge between the storage capacitors.

The switches turn on and off at a 250 kHz rate, which is gener-

ated from an internal 500 kHz oscillator. The basic principle

behind the voltage inversion scheme is illustrated in Figures 11

and 12.

S2

S1

S3

S4

+

–

Figure 11. ADP3605 Switch Configuration Charging the

Pump Capacitor

During phase one, S1 and S2 are ON, charging the pump ca-

pacitor to the input voltage. Before the next phase begins, S1

and S2 are turned OFF as well as S3 and S4 to prevent any

overlap. S3 and S4 are turned ON during the second phase (see

Figure 12) and charge stored in the pump capacitor is trans-

ferred to the output capacitor.

+

–

S2

S1

S3

S4

Figure 12. ADP3605 Switch Configuration Charging the

Output Capacitor

During the second phase, the positive terminal of the pump

capacitor is connected to ground through variable resistance

switch, S3, and the negative terminal is connected to the out-

put, resulting in a voltage inversion at the output terminal.

The ADP3605 block diagram is shown on the front page.

APPLICATION INFORMATION

Capacitor Selection

The ADP3605’s high internal oscillator frequency permits the

use of small capacitors for both the pump and the output ca-

pacitors. For a given load current, factors affecting the output

voltage performance are:

When selecting the capacitors, keep in mind that not all manu-

facturers guarantee capacitor ESR in the range required by the

circuit. In general, the capacitor’s ESR is inversely proportional

to its physical size, so larger capacitance values and higher volt-

age ratings tend to reduce ESR. Since the ESR is also a function

of the operating frequency, when selecting a capacitor, make

sure its value is rated at the circuit's operating frequency.

Temperature is another factor affecting capacitor performance.

Figure 13 illustrates the temperature effect on various capaci-

tors. If the circuit has to operate at temperatures significantly

different from 25

°C, the capacitance and ESR values must be

carefully selected to adequately compensate for the change.

Various capacitor technologies offer improved performance over

temperature; for example, certain tantalum capacitors provide

good low-temperature ESR but at a higher cost. Table II pro-

vides the ratings for different types of capacitor technologies to

help the designer select the right capacitors for the applica-

ever, low ESR capacitors such as solid tantalum and multilayer

ceramic capacitors are recommended to minimize voltage loss at

high currents. Table III shows a partial list of the recommended

low ESR capacitor manufacturers.

Input Capacitor

A small 1

µF input bypass capacitor, preferably with low ESR,

such as tantalum or multilayer ceramic, is recommended to

reduce noise and supply transients and supply part of the peak

input current drawn by the ADP3605. A large capacitor is rec-

ommended if the input supply is connected to the ADP3605

through long leads, or if the pulse current drawn by the device

might affect other circuitry through supply coupling.

Output Capacitor

minimize ripple on the output. Figure 14 illustrates the output

ripple voltage effect for various capacitance and ESR values.

Note that as the capacitor value increases beyond the point

where the dominant contribution to the output ripple is due to

added capacitance. Since output current is supplied solely by

cycle, peak-to-peak output ripple voltage is calculated by using

the following formula.

V

I

FC

I

ESR

RIPPLE

L

SO

LCO

=

××

+×

×

2

2

where:

V

mA

kHz

F

mA

mV

××

+×

×

=

120

2

250

10

2

120

0 15

60

µ

.

Multiple smaller capacitors can be connected in parallel to yield

lower ESR and lower cost. For lighter loads, proportionally

smaller capacitors are required. To reduce high frequency

noise, bypass the output with a 0.1

µF ceramic capacitor in

parallel with the output capacitor.