ADP3607 datasheet(7/8 Pages) AD

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REV. 0

ADP3607

–7–

the output capacitor, CO, during one-half of the charge-pump

cycle, peak-to-peak output ripple voltage is calculated by using

the following formula.

ESR

RIPPLE

PUMP

LCO

××

+× ×

where

IL = Load Current

FPUMP = 250 kHz nominal switching frequency

CO = 10

µF with an ESR of 0.15 Ω

kHz

RIPPLE

××

+×

2 250

250

0 15

= 25 mV

Multiple smaller capacitors can be connected in parallel to yield

lower ESR and potential cost savings. For lighter loads, propor-

tionally smaller capacitors are required. To reduce high frequency

noise, bypass the output with a 0.1

µF ceramic capacitor in parallel

with the output capacitor.

Pump Capacitor

The ADP3607 alternately charges CP to the input voltage when

CP is switched in parallel with the input supply, and then trans-

fers charge to CO when CP is switched in parallel with CO. Dur-

ing the time CP is charging, the peak current is approximately

two times the output current. During the time CP is delivering

charge to CO, the supply current drops down to about 3 mA.

A low ESR capacitor has much greater impact on performance

for CP than CO since current through CP is twice the CO cur-

rent. Therefore, the voltage drop due to CP is about four times

the ESR of CP times the load current. While the ESR of CO

affects the output ripple voltage, the voltage drop generated by

the ESR of CP, combined with the voltage drop due to the out-

put source resistance, determines the maximum available VOUT.

Improved Load Regulation

In most applications, IR drops due to printed circuit board

traces are not critical. VSENSE should be connected to the output

at a convenient pcb location close to the load. However, if a

reduction in IR drops, or improvement in load regulation is

desired, the sense line can be used to monitor the output voltage

at the load. To avoid excessive noise pickup, keep the VSENSE

line as short as possible and away from any noisy line.

Shutdown Mode

The ADP3607’s output can be disabled by pulling the SD Pin

to a TTL /CMOS logic high level which will stop the internal

oscillator. Applying a logic low will turn ON the oscillator. If

the shutdown feature is not used, the SD pin should be tied to

ground. The shutdown mode current is dominated by the resis-

tor divider connected to the VSENSE pin. This current can be

calculated using one of the following formulas.

5 V fixed output version:

SENSE SD

()

(

–.

)

23 75

Ω

Adjustable output version:

SENSE SD

EXT

()

(

–.

)

Ω

where R

EXT is in k

Ω.

Because of the external Schottky diode between VIN and VOUT,

the output voltage will be held to a diode drop below VIN when

the ADP3607 is in shutdown mode.

Power Dissipation

The power dissipation of the ADP3607 circuit must be limited

such that the junction temperature of the device does not exceed

the maximum junction temperature rating. Total power dissipa-

tion is calculated as follows:

P = (2 VIN – VOUT) IOUT + (VIN) IS

Where IOUT and IS are output current and supply current, VIN

and VOUT are input and output voltages respectively.

For example: assuming worst case conditions, VIN = 5 V,

VOUT = 5 V, IOUT = 50 mA and IS = 6 mA. Calculated device

power dissipation is:

≈ (2 × 5 V – 5 V)(0.05 A) + (5 V)(0.006 A) = 280 mW

This is far below the 660 mW power dissipation capability of the

ADP3607.

General Board Layout Guidelines

Since the ADP3607’s internal switches turn on and off very

quickly, good PC board layout practices are critical to ensure

optimal operation of the device. Improper layouts will result in

poor load regulation, especially with heavy loads. Following

these simple layout guidelines will improve output performance.

1. Use adequate ground and power traces or planes.

2. Use single point ground for device ground and input and

output capacitor grounds.

3. Keep external components as close to the device as possible.

4. Use short traces from the input and output capacitors

to the input and output pins respectively.

Maximum Output Voltage

Maximum unregulated output voltage can be obtained by con-

necting the VSENSE pin to ground instead of to the VOUT pin (see

Figure 18). Under this condition, the magnitude of the unregu-

lated output voltage depends on the load current. VOUT is

inversely proportional to the load current.

OUTPUT CURRENT – mA

5.5

540

5.7

5.9

6.1

6.3

6.5

6.7

6.9

7.1

7.3

VIN = 3.6V

VIN = 3.3V

VIN

4.7 F

CIN

4.7 F

VSENSE

VIN

CP+

CP–

VOUT

GND

IN5819

Figure 18. Maximum Unregulated Output Voltage

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