REV. 0

ADP3170

–11–

R

RR

R

R

kM

k

k

A

T

OGM

B

A

=

==

1

11

1

1

1

888

1

1

1

29 7

12 83

––

.

––

.

.

ΩΩ

Ω

Ω

(13)

The required equivalent series resistance (ESR) and capacitance

drive the selection of the type and quantity of the output capaci-

tors. The ESR of the output filter capacitor bank must be equal

to or less than the specified output resistance of the voltage

regulator (3.2 m

Ω). The capacitance must be large enough that

the voltage across the capacitor, which is the sum of the resistive

and capacitive voltage drops, does not move below or above the

initial resistive step while the inductor current ramps up or

down to the value corresponding to the new load current. One

can use, for example, eight ZA series capacitors from Rubycon,

which have a maximum ESR of 24 m

Ω. These eight 1000 µF

capacitors would give an ESR of 3 m

Ω.

As long as the capacitance of the output capacitor is above a

critical value, and the regulating loop is compensated with

Analog Devices’ proprietary compensation technique (ADOPT),

the actual value has no influence on the peak-to-peak deviation

of the output voltage to a full step change in the load current.

The critical capacitance can be calculated as follows:

The equivalent capacitance of the eight ZA series Rubycon

capacitors is 8

× 1 mF = 8 mF. In this case, the total capacitance

is safely above the critical value.

Feedback Loop Compensation Design for ADOPT

Optimized compensation of the ADP3170 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

The output current slew rate of any practical switching power

converter is inherently limited by the inductor to a value much

less than the slew rate of the load. Therefore, any sudden change

of load current will initially flow through the output capacitors,

and assuming that the capacitance of the output capacitor is

larger than the critical value defined by Equation 14, this will

produce a peak output voltage deviation equal to the ESR of the

output capacitor times the load current change.

The optimal implementation of voltage positioning, ADOPT,

will create an output impedance of the power converter that is

entirely resistive over the widest possible frequency range,

including dc, and equal to the specified dc output resistance.

With the wide-band resistive output impedance the output

voltage will droop in proportion with the load current at any

load current slew rate; this ensures the optimal positioning

and allows the minimization of the output capacitor.

With an ideal current-mode controlled converter, where the

inductor current would respond without delay to the command

signal, the resistive output impedance could be achieved by

having a single-pole roll-off of the voltage gain of the voltage-

error amplifier. The pole frequency must coincide with the ESR

zero of the output capacitor.

The ADP3170 uses peak-current control, which is known to

have a nonideal, frequency-dependent command signal-to-

inductor current transfer function. The frequency dependence

manifests in the form of a pair of complex conjugate poles at

one-half of the switching frequency. A purely resistive output

impedance could be achieved by canceling the complex conju-

gate with zeros at the same complex frequencies and adding a

third pole equal to the ESR zero of the output capacitor. Such a

compensating network would be quite complicated. Fortu-

nately, in practice, it is sufficient to cancel the pair of complex

conjugate poles with a single real zero placed at one-half of the

switching frequency.

Although the end result is not a perfectly resistive output imped-

ance, the remaining frequency dependence causes only a slight

percentage of deviation from the ideal resistive response. The

single-pole and single-zero compensation can be easily imple-

the capacitance and resistance of the series RC network are

calculated as follows:

C

C

ESR

R

C

mF

m

k

nF

OC

OUT

T

OC

=

×

=

×Ω

Ω

=

83

888

27

.

.

(15)

The closest standard value is 2.7 nF. The series resistance is:

R

Cf

R

nF

kHz

Z

OC

MIN

Z

=

××

=

××

=Ω

2

2

2 7

188

1255

π

π

.

(16)

The nearest standard 5% resistor value is 1.2 k

Ω. Note that this

therefore be omitted.

C

I

RV

V

L

C

A

mV

mV

HmF

OUT CRIT

O

OUT

OUT

OUT CRIT

()

()

(–)

.( .

[–

])

.

=

×+

×

=

×+

×=

23

32

18

29

14 06

Ω

µ

(14)