ADP3088

–10–

REV. PrK

PRELIMINARY TECHNICAL DATA

output voltage within a ~100 mV range with only a 4.7

µF

output capacitor, even when the load slew rate is extremely

fast. This does not include the initial tolerance of the volt-

age setting that is separately accounted with voltage posi-

feedback divider is reduced from the 10 k

Ω value that one

would use for a standard (non-voltage-positioned) design

SW

DRV

FB

IN

GND

COMP

ADP3088

-2.5V

100-400 mA

3.3

µH

RA

10k

Ω

RB

8.75k

Ω

1A

SCHOTTKY

IN

GND

4.7µF

MLCC

CHF

4.7pF

1µF

MLCC

3.3V

RVP

51k

Ω

Figure 4. Application Circuit using Voltage Positioning,

Allowing Small Output Capacitance

Extra-Low-Voltage Outputs

Some newer power management applications require volt-

age levels below the normal adjustable voltage range of the

ADP3088, i.e., below 1.25 V. Such applications can be

accommodated using the ADP3088 by modifying the appli-

cation circuit to sum in a resistor-weighted portion of an-

other regulated system voltage, e.g., 3.3 V, to the feedback

node (FB). The tolerance of the ADP3088's output voltage

will increase by an amount proportional to the tolerance of

the summed in system voltage times the ratio of the con-

ductance from that node to that of the output voltage. The

below example in Figure 5 shows an implementation of this

technique together with another special implementation

tem voltage to the FB node that will reduce the output volt-

age according to the formula:

A

OUT

TT

TT

R

VV

R

∆= −

×

(19)

Dynamic Voltage Control

Some newer power management applications also require

an ability to adjust the voltage being delivered to a load

during operation. Although there is no integration of this

feature in the ADP3088, it can readily be accommodated

with a few components. Dynamic voltage control can be

implemented either by parallel bus control or by PWM. In

both cases, the output voltage is modified by summing

either switched bits with, presumably binary, weighting

resistors or a switched PWM node via a single resistor into

the FB pin. (The switched PWM node refers to an external

PWM control signal, not the switched node of the power

converter itself.) Since the PWM technique modulates a

current into the FB node, it is necessary both to integrate

that signal and to avoid slowing down the response of the

power converter to output voltage transitions. This can be

accomplished by placing a capacitor between the output

voltage and the feedback node, which serves to provide a

zero/pole pair in the main regulation loop, and appears as

an integration pole to the PWM signal.

The design of either parallel bit or PWM type of voltage

control must consider whether the interface node(s) - from

parallel switched bits or a single PWM signal - has an active

pullup state (in which case it must be to a known voltage)

or a passive pullup (open drain) that floats up to the FB

node voltage, 1.25 V, in its high state. If at least the lower

extreme of the desired output voltage range must be lower

than 1.25 V, either technique can be combined with the

technique for lowering the output voltage below 1.25 V.

Such an example of an application having this requirement

is the BlackFin™ DSP. Figure 5 shows an implementation

of this technique.

Input Voltage: 4.75 V ~ 7.5 V

Output Voltage: 0.9 V ~ 1.5 V

Dynamic voltage control interface technique: PWM,

System voltage used for lowering output voltage below

Maximum output current: 700 mA

Figure 5. BlackFin DSP Application

SW

DRV

FB

IN

GND

COMP

ADP3088

VOUT

0.9V-1.5V

@700 mA

10

µH @ 1A

RA

10.0k

Ω

RPWM

41.2k

Ω

1N5817

IN

GND

3

×10µF

MLCC

CHF

10pF

2.2µF

MLCC

VIN

5V - 8V

RC

20k

Ω

CC

470pF

VTT 2.5V

RTT

287k

Ω

CFF

2.2nF

PWM 0-2.5V